US2010290466A1PendingUtilityA1

Routing of data streams

Assignee: ST MICROELECTRONICS LTDPriority: Feb 24, 2003Filed: May 17, 2010Published: Nov 18, 2010
Est. expiryFeb 24, 2023(expired)· nominal 20-yr term from priority
Inventors:Matt Morris
H04L 49/103H04L 49/25
42
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Claims

Abstract

The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Claims

exact text as granted — not AI-modified
1 . A method for delivering incoming packets to at least one destination, comprising:
 mapping at least one source to at least one destination;   associating a source and at least one destination for a particular packet with a memory location at which the particular packet is stored; and   controlling removal of the incoming packets from a memory to at least on destination wherein the incoming packets have a lower bit-rate than packets delivered to the at least one destination.   
     
     
         2 . A method for controlling removal of packets from a memory to at least one destination, comprising:
 reading each packet from a memory;   determining a number of particular destinations to which each read packet is destined for delivery;   checking whether a port for each particular destination is available;   if the packet is destined for delivery to more than one particular destination, outputting the packet for multi-destination delivery only if a port for each of the particular destinations is simultaneously available; and   if the packet is destined for delivery to only one particular destination, outputting the packet only when a port for ht at particular destination is available.   
     
     
         3 . An apparatus for controlling removal of packets from a memory at least one destination, comprising:
 a processor for reading each packet from a memory and determining a number of particular destinations to which each read packet is destined for delivery; and   a plurality of outputs for receiving the read packet, wherein if the packet is destined for delivery to more than one particular destination, each output in the plurality of outputs receiving the packet only if a port for each of the particular destinations is simultaneously available.

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