Semiconductor device having reduced die-warpage and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.

1 . A method of manufacturing a semiconductor device, comprising:
 providing a chip-sized substrate; and   forming a first layer of material in at least two discrete sections over substantially the entire surface of the substrate, wherein the sections are partitioned from one another by a stress-relieving pattern that traverses the first layer of material and by which stress otherwise applied to the substrate by the first layer is mitigated.   
     
     
         2 . The method of  claim 1 , wherein the forming of the first layer of material comprises forming the at least two discrete sections of the first layer of material in contact with each other, such that the interface between the at least two discrete sections constitutes the stress-relieving pattern. 
     
     
         3 . The method of  claim 2 , wherein the forming of the first layer of material comprises forming an initial layer of material over the surface of the substrate, subsequently removing a portion of the initial layer of material from over a region of the substrate, and subsequently depositing the same type of material as the initial layer onto the region of the substrate from which said portion of the initial layer had been removed. 
     
     
         4 . The method of  claim 1 , wherein the forming of the first layer of material comprises sequentially forming the discrete sections of the first layer of material over respective regions of the substrate. 
     
     
         5 . The method of  claim 1 , wherein the first layer is an interlayer insulating layer, a passivation layer or a photosensitive polyimide layer. 
     
     
         6 . The method of  claim 1 , further comprising:
 forming a second layer of material in at least two discrete sections over substantially the entire surface of the first layer, wherein the sections of the second layer of material are partitioned from one another by a stress-relieving pattern that traverses the second layer of material.   
     
     
         7 . The method of  claim 6 , wherein each of the stress-relieving patterns is made up of at least one segment that traverses the respective layer in which it exists, and the second layer is formed such that at least one segment of the stress-relieving pattern in the second layer is offset with respect to the stress-relieving pattern in the first layer. 
     
     
         8 . The method of  claim 7 , wherein the second layer of material is formed such that none of the segments of the stress-relieving pattern in the second layer of material is vertically aligned with any of the segments of the stress-relieving pattern in the first layer of material. 
     
     
         9 . A method of manufacturing a semiconductor device, comprising:
 providing a chip-sized semiconductor substrate; and   forming a first layer of material over substantially the entire surface of the semiconductor substrate;   patterning the first layer to form at least one trench that traverses the first layer and partitions the first layer into at least two discrete sections; and   filling the trench with a material that is different from the material of the first layer, thereby forming a stress-relieving pattern by which stress otherwise applied to the substrate by the first layer is mitigated.   
     
     
         10 . The method of  claim 9 , wherein the first layer is one of an interlayer insulating layer, a passivation layer and a photosensitive polyimide layer. 
     
     
         11 . The method of  claim 9 , further comprising:
 forming a second layer of material in at least two discrete sections over substantially the entire surface of the first layer of material, wherein the sections of the second layer are partitioned from one another by a stress-relieving pattern that traverses the second layer of material and by which stress otherwise applied to the substrate by the second layer via the first layer is mitigated.   
     
     
         12 . The method of  claim 11 , wherein the forming of the second layer comprises forming an initial layer of material over the first layer of material, which initial layer fills the trench and thereby forms the stress-relieving pattern in the first layer of material. 
     
     
         13 . The method of  claim 11 , wherein each of the stress-relieving patterns is made up of at least one segment that traverses the respective layer in which it exists, and the second layer is formed such that at least one segment of the stress-relieving pattern in the second layer is offset with respect to the stress-relieving pattern in the first layer. 
     
     
         14 . The method of  claim 13 , wherein the second layer of material is formed such that none of the segments of the stress-relieving pattern in the second layer of material is vertically aligned with any of the segments of the stress-relieving pattern in the first layer of material. 
     
     
         15 . A method of manufacturing a semiconductor device, comprising:
 providing a chip-sized substrate on which a plurality of connection pads are exposed, and in which a plurality of fuse lines run at a level beneath the connect pads;   forming a passivation layer over substantially the entire surface of the substrate; and   forming a layer of a photosensitive polyimide in at least two discrete sections over substantially the entire surface of the passivation layer, wherein the sections are partitioned from one another by a stress-relieving pattern that traverses the photosensitive polyimide layer and by which stress otherwise applied to the substrate by the first layer is mitigated; and   forming a plurality of through-holes that extend through the passivation layer and the photosensitive polyimide layer and expose the connection pads and the fuse lines.   
     
     
         16 . The method of  claim 15 , wherein the forming of the through-holes comprises:
 forming a mask on the passivation layer, the mask having a pattern corresponding to the pattern of the through-holes; and   etching the passivation layer and the substrate using the mask as an etch mask.   
     
     
         17 . The method of  claim 15 , wherein the forming of the photosensitive polyimide layer and the through-holes comprises:
 forming an initial layer of photosensitive polyimide over substantially the entire surface of the passivation layer;   patterning the initial layer of photosensitive polyimide to form through-holes that extend through the initial layer of photosensitive polyimide layer as aligned with the pad connections and fuse lines, and to form trenches that extend through the initial layer of photosensitive polyimide layer; and   filling the trenches to form the stress-relieving pattern.   
     
     
         18 . The method of  claim 17 , wherein the trenches are formed as connecting at least some of the through-holes that extend through the photosensitive polyimide layer. 
     
     
         19 . A method of manufacturing a semiconductor device, comprising:
 designing a die of a semiconductor device comprising a chip-sized substrate and a plurality of layers stacked on and extending over substantially the entire surface of the substrate, wherein design parameters of the device include the thickness of the substrate, the thicknesses of the layers that are to be stacked on the substrate, and the materials from which the substrate and the layers are to be fabricated;   before the die of the semiconductor device is fabricated, characterizing warpage that the die, fabricated according to said design parameters, will exhibit as the result of stress applied to the substrate by the layers stacked on the substrate; and   subsequently fabricating the die according to the design parameters, including by forming one of the layers on the substrate in at least two discrete sections as partitioned from one another by a stress-relieving pattern based on the characterization of the warpage so as to mitigate the stress otherwise applied to the substrate in the die.   
     
     
         20 . The method of  claim 19 , wherein the characterizing of the warpage that the die will exhibit comprises quantifying the relative difference in height that will exist between edges of the die and a central portion of the die. 
     
     
         21 . The method of  claim 19 , wherein the forming of said one of the layers on the substrate comprises forming the at least two discrete sections of the layer in contact with each other, such that the interface between the at least two discrete sections constitutes the stress-relieving pattern. 
     
     
         22 . The method of  claim 19 , wherein the forming of said one of the layers on the substrate comprises forming a trench that partitions the layer into at least two discrete sections, and filling the trench with a material that is different from the material of the layer.