US2010285649A1PendingUtilityA1

Field-Effect Heterostructure Transistors

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Individually held — no corporate assignee on recordPriority: Sep 25, 2006Filed: Jun 11, 2010Published: Nov 11, 2010
Est. expirySep 25, 2026(~0.2 yrs left)· nominal 20-yr term from priority
Inventors:Robert L. Willett
H10P 32/14H10P 10/00H10D 30/471H10D 30/015H10D 64/519H10D 64/518H10D 62/822H10D 30/47H10D 64/27
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Claims

Abstract

An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.

Claims

exact text as granted — not AI-modified
1 - 9 . (canceled) 
     
     
         10 . A method of forming a transistor, comprising:
 providing a region of first inorganic semiconductor on a layer of second inorganic semiconductor, the region and layer forming a semiconductor heterostructure;   forming source and drain electrodes for the transistor on the semiconductor heterostructure;   depositing a dielectric layer over parts of the source and drain electrodes and over a channel part of the semiconductor heterostructure located between the source and drain electrodes; and   forming a gate electrode for the transistor vertically over the channel part of the semiconductor heterostructure between the source and drain electrodes and vertically over parts of the source and, drain electrodes; and   wherein the gate electrode and parts of the source and drain electrodes are located over a same side of the layer and are located over a same side of the region; and   wherein the method forms transistor capable of trapping a two-dimensional charge carrier gas in the channel part of the semiconductor heterostructure.   
     
     
         11 . The method of  claim 10 , further comprising:
 causing conductive material to diffuse from the source and drain electrodes into the semiconductor heterostructure.   
     
     
         12 . The method of  claim 10 ,
 wherein the gate electrode is located on the dielectric layer.   
     
     
         13 . The method of  claim 12 , further comprising:
 causing conductive material to diffuse from the source and drain electrodes into the semiconductor heterostructure.   
     
     
         14 . The method of  claim 10 , wherein the providing a semiconductor heterostructure includes epitaxially growing the layer of second inorganic semiconductor on a surface of the region of first inorganic semiconductor. 
     
     
         15 . The method of  claim 14 , wherein the first and second semiconductors include gallium and arsenic. 
     
     
         16 . The method of  claim 15 , wherein one of the first semiconductor and the second semiconductor includes aluminum. 
     
     
         17 . The method of  claim 16 , wherein the one of the first semiconductor and the second semiconductor has a ratio atoms of the aluminum to atoms of the gallium atoms, the ratio being x/(1−x), 0.1<x<0.25. 
     
     
         18 . The method of  claim 16 ,
 wherein the gate electrode is located on the dielectric layer.   
     
     
         19 . The method of  claim 18 , further comprising:
 causing conductive material to diffuse from the source and drain electrodes into the semiconductor heterostructure.

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