Semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.

1 - 22 . (canceled) 
     
     
         23 . A semiconductor memory device for storing information on a memory cell using a potential change in a word line and a bit line, the semiconductor memory device comprising:
 a memory cell having a circuit configuration in which a potential supplied to the word line is different from at least one of a potential supplied to a source of a load transistor included in a latch section and a potential supplied to the bit line; and   a first control circuit for switching a first operation mode and a second operation mode to each other in accordance with a signal applied to a mode setting pin,   wherein the potential supplied to the word line corresponding to at least one of the potential supplied to the source of the load transistor and the potential supplied to the bit line, and the potential supplied to the word line in a ON state, are different from a potential in the first operation mode, during an arbitrary period of at least a read operation in the second operation mode.   
     
     
         24 . The semiconductor memory device according to  claim 23 , further comprising a second control circuit for controlling the potential supplied to the word line corresponding to at least one of the potential supplied to the source of the load transistor and the potential supplied to the bit line, and the potential supplied to the word line in a ON state to be higher than a potential in the first operation mode, during an arbitrary period of at least a read operation in the second operation mode.