Static random accee memory device

Abstract

Additional transistors P 1 and P 2 which are PMOS transistors are connected to load transistors PL 1 and PL 2 which are PMOS transistors such that drain electrodes of the additional transistors P 1 and P 2 and drain electrodes of the load transistors PL 1 and PL 2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P 1 and P 2 and gate electrodes of the load transistors PL 1 and PL 2 are connected at the node 1 and the node 2 . A source electrode of the additional transistor P 1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S 1 and S 2 to the H level in other times than data write so that the additional transistor P 1 or P 2 compensates the load transistor PL 1 or PL 2 , thereby increasing the static margin. In data write, the additional transistor control circuit sets the control signals S 1 and S 2 to the low level, thereby preventing the additional transistors from hindering the data write, and thus increasing the write margin.

1 . A static random access memory device comprising:
 a plurality of bit line pairs, each of said bit line pairs comprising a first bit line and a second bit line;   a plurality of word lines, said plurality of word lines and said plurality of bit line pairs being arranged in a matrix;   a plurality of static random access memory cells each arranged corresponding to each node of said matrix, each of a said plurality of said static random access memory cells comprising:
 a first CMOS inverter comprising a first PMOS transistor and a first NMOS transistor, drains of said first PMOS and NMOS transistors being coupled to a first node, gates of said first PMOS and NMOS transistors being coupled to a second node; 
 a second CMOS inverter comprising a second PMOS transistor and a second NMOS transistor, drains of said second PMOS and NMOS transistors being coupled to said second node, gates of said second PMOS and NMOS transistors being coupled to said first node; 
 a first access transistor comprising one of source/drain being coupled to said first node, the other of source/drain being coupled to a corresponding first bit line of corresponding bit line pairs of said plurality of bit line pairs, and a gate being coupled to a corresponding word line of sad plurality of word lines; 
 a second access transistor comprising one of source/drain coupled to said second node, the other of source/drain being coupled to a corresponding second bit line of a said corresponding bit line pairs, and a gate being coupled to said corresponding word line; 
 a first additional transistor comprising one of source/drain coupled to said first node, and a gate coupled to said second node; and 
 a second additional transistor comprising one of source/drain coupled to said second node, and a gate coupled to said first node, 
 wherein said first and second PMOS transistors and said first and second additional transistors are formed in a same well. 
   
     
     
         2 . The static random access memory device of  claim 1 , wherein each of said additional transistor control circuits is configured to receive a write enable signal, a corresponding column select signal, and a data input signal, and to generate each control signals for said first and second additional transistors. 
     
     
         3 . The static random access memory device of  claim 1 , wherein each of said plurality of additional transistor control circuit is arranged corresponding to each of said plurality of bit line pairs, and is configured to control a plurality of static random access memory cells coupled to a corresponding bit line pairs. 
     
     
         4 . The static random access memory device of  claim 1 ,
 wherein each of said first and second access transistor comprises an NMOS transistor, and each of said first and second additional transistor comprises a PMOS transistor.   
     
     
         5 . The static random access memory device of  claim 1 , wherein said static random access memory device comprises a dual port memory device, each of said bit line pairs being a first bit line pairs, and each of said word lines being a first word line, and
 wherein said static random access memory device further comprises:
 a plurality of second bit line pairs, each of said second bit line pairs comprising a third bit line and a forth bit line, said third and forth bit lines being corresponding to said first and second bit lines; and 
 a plurality of second word line, each of said second word line being corresponding to said first word line; and 
   wherein each of said static random access memory cells further comprises:
 a third access transistor comprising one of source/drain coupled to said first node, the other of source/drain coupled to a corresponding third bit line, and a gate coupled to a corresponding second word line; and 
 a forth access transistor comprising one of source/drain coupled to said second node, the other of source/drain coupled to a corresponding forth bit line, and a gate coupled to said corresponding second worse line. 
   
     
     
         6 . The static random access memory device of  claim 1 , wherein each of said additional transistor control circuits is configured to receive a write enable signal, a corresponding column select signal, and a data input signal, and to generate each control signals for said first and second additional transistors. 
     
     
         7 . The static random access memory device of  claim 1 , wherein each of said plurality of additional transistor control circuit is arranged corresponding to each of said plurality of first bit line pairs, and is configured to control a plurality of static random access memory cells coupled to a corresponding bit line pairs. 
     
     
         8 . The static random access memory device of  claim 1 ,
 wherein each of said first to fourth access transistors comprises an NMOS transistor, and each of said first and second additional transistors comprises a PMOS transistor.