Multi-bank memory

Abstract

A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.

1 . A memory device comprising:
 memory cores from different banks interleaved in a strip in an alternating fashion; and   sense amplifiers shared between the different banks.   
     
     
         2 . The memory device of  claim 1 , wherein memory cores from different banks interleaved within rows in an alternating fashion. 
     
     
         3 . The memory device of  claim 1 , wherein memory cores from different banks interleaved within columns in an alternating fashion. 
     
     
         4 . The memory device of  claim 1 , wherein sense amplifiers are shared between two different banks in the strip. 
     
     
         5 . The memory device of  claim 1 , wherein each sense amp is coupled to two cores, each core from a different bank. 
     
     
         6 . A memory device comprising:
 memory cores from different banks interleaved in a number of rows in an alternating fashion;   sense amplifiers shared between the different banks; and   a single column decoder associated with each row in the number of rows.   
     
     
         7 . The memory device of  claim 6 , wherein each row in the number of rows supports only one access at a time. 
     
     
         8 . The memory device of  claim 6 , wherein each column decoder is associated with two banks. 
     
     
         9 . The memory device of  claim 6 , wherein each row includes more than two memory cores. 
     
     
         10 . The memory device of  claim 6 , wherein two memory cores are associated with a sense amplifier. 
     
     
         11 . A memory device comprising:
 memory cores from different banks interleaved in a number of columns in an alternating fashion;   sense amplifiers shared between the different banks; and   a single row decoder associated with each column in the number of columns.   
     
     
         12 . The memory device of  claim 11 , wherein each column in the number of columns supports only one access at a time. 
     
     
         13 . The memory device of  claim 11 , wherein each row decoder is associated with two banks. 
     
     
         14 . The memory device of  claim 11 , wherein each column includes more than two memory cores. 
     
     
         15 . The memory device of  claim 11 , wherein two memory cores are associated with a sense amplifier. 
     
     
         16 . A memory device comprising:
 a two dimensional array of memory cores;   wherein, memory cores from different banks are interleaved in multiple strips along a first dimension in an alternating fashion;   wherein one or more strips along the first dimension includes a sense amplifier shared between different banks; and   wherein memory cores from different banks are not interleaved in a second direction, orthogonal to the first dimension.   
     
     
         17 . The memory device of  claim 16 , wherein memory cores from different banks are interleaved in multiple rows, and wherein memory cores from different banks are not interleaved in columns. 
     
     
         18 . The memory device of  claim 16 , wherein memory cores from different banks are interleaved in multiple columns, and wherein memory cores from different banks are not interleaved in rows. 
     
     
         19 . The memory device of  claim 16 , wherein two or more strips are configured to be accessed in parallel. 
     
     
         20 . The memory device of  claim 16 , wherein each strip includes a single decoder.