I/O Buffer Circuit

Abstract

An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( 10 ) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

1 . An input buffer circuit ( 102 ), comprising:
 a voltage level limiter circuit ( 501 ) receiving a first input signal from a pad and limiting a voltage level of the input signal to output a second input signal to a first terminal;   a voltage level pull-up circuit ( 503 ) coupled to the first terminal, pulling up a voltage level of the first terminal (Vi 1 ) to a third specific voltage level;   an inverter ( 502 ) coupled to the first terminal and inverting the second input signal to generate a third input signal; and   an input stage circuit ( 504 ) receiving the third signal and inverting the third signal to generate a fourth input signal for a second core circuit ( 20 ).   
     
     
         2 . The input buffer circuit as claimed in  claim 1 , wherein the voltage level pull-up circuit ( 503 ) pulls up the voltage level of the first terminal when a voltage level of the third signal is at a low voltage level. 
     
     
         3 . The input buffer circuit as claimed in  claim 1 , wherein the voltage level pull-up circuit ( 503 ) is coupled between the inverter and the voltage level limiter circuit, and pulls up the voltage level of the first terminal according to a voltage level of the third signal. 
     
     
         4 . The input buffer circuit as claimed in  claim 1 , wherein the input buffer circuit converts a first voltage range of the first input signal into a second voltage range of the fourth input signal for the second core circuit. 
     
     
         5 . The input buffer circuit as claimed in  claim 1 , wherein the voltage level limiter circuit ( 501 ) comprises a second NMOS transistor, the second NMOS transistor comprises a gate coupled to a supply voltage (VDD) and is coupled between the pad and the inverter, and the second core circuit operates normally under the supply voltage.