Variable delay circuit, variable delay device, and vco circuit

Abstract

Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.

1 . A variable delay circuit, comprising:
 a first delay portion that delays an input signal;   an output portion;   a variable impedance portion coupled between the first delay portion and the output portion; a path not including the first delay portion; and   a second delay portion that generates a delay time smaller than a delay time generated by the first delay portion provided in the path.   
     
     
         2 . The variable delay device of  claim 1 , further comprising:
 a first path without the first delay portion and a second path via the variable impedance portion, wherein the signal path through the variable delay device can be switched between the first path and the second path.   
     
     
         3 . A method for generating delay in a delay locked loop (DLL) portion, comprising:
 adjusting an impedance in a first variable impedance portion to a first impedance based on a first bias voltage;   adjusting an impedance in a second variable impedance portion to a second impedance based on a second bias voltage; and   generating and outputting a delay based on the first impedance and the second impedance.   
     
     
         4 . The method of  claim 3 , further comprising:
 supplying the first bias voltage to make the first impedance a minimum value; and   supplying the second bias voltage to make the second impedance a maximum value.   
     
     
         5 . The method of  claim 3 , further comprising:
 supplying the first bias voltage to make the first impedance a maximum value or a minimum value; and   supplying the second bias voltage to make the second impedance a maximum value when the first impedance is the maximum value and to make the second impedance a minimum value when the first impedance is a minimum value.   
     
     
         6 . The method of  claim 3 , further comprising:
 adjusting a first impedance and a second impedance in a first delay circuit to generate a first delay;   adjusting the first impedance and the second impedance in a second delay circuit to generate a second delay; and   selecting at least one of the first delay and the second delay.