Semiconductor integrated circuit, d-a converter device, and a-d converter device

Abstract

A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

1 - 12 . (canceled) 
     
     
         13 . A semiconductor integrated circuit, comprising:
 a plurality of capacitor cells arranged in an N×M matrix each having a first electrode formed in a first conductive layer and a second electrode formed in a second conductive layer above the first conductive layer; and   a wiring formed in a layer of at least one of the first conductive layer and the second conductive layer between at least two capacitor cells of the plurality of capacitor cells,   wherein the wiring surrounds at least one of said plurality of capacitor cells.   
     
     
         14 . The semiconductor integrated circuit according to  claim 13 ,
 wherein the plurality of capacitor cells is arranged in a 2×2 matrix.   
     
     
         15 . A semiconductor integrated circuit, comprising:
 a plurality of capacitor cells arranged in an N×M matrix each having a first electrode formed in a first conductive layer and a second electrode formed in a second conductive layer above the first conductive layer; and   a wiring formed in a layer of at least one of the first conductive layer and the second conducive layer between at least two capacitor cells of the plurality of capacitor cells, wherein the wiring is disposed between each of the plurality of capacitor cells.   
     
     
         16 . The semiconductor integrated circuit according to  claim 15 ,
 wherein the plurality of capacitor cells is arranged in a 2×2 matrix.