Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof

Abstract

One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.

1 . A semiconductor device, comprising:
 transistors located over a semiconductor substrate;   a pre-metal dielectric layer located over the transistors;   electrical contacts located in the pre-metal dielectric layer that electrically contact the transistors;   ferroelectric random access memory (FeRAM) capacitors located over the pre-metal dielectric layer, including:
 a first barrier layer located over the electrical contacts and the pre-metal dielectric layer, wherein the first barrier layer is a stack of multiple barrier layers having a same elemental composition and interfaces located therebetween; 
 a second barrier layer located over the first barrier layer, the second barrier layer having an elemental composition different from the first barrier layer; 
 a lower capacitor electrode located over the stack; 
 a ferroelectric dielectric layer located over the lower capacitor; and 
 an upper capacitor electrode located over the ferroelectric dielectric layer; 
   interlevel dielectric layers located over the FERAM capacitors; and   interconnects located over and within the interlevel dielectric layers that interconnect the transistors and capacitors.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the stack is a titanium nitride stack of barrier layers and has an atomic percent of carbon of less than about 4.5% and an atomic percent of oxygen of less than about 2.4% and includes two or more layers. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the stack has an atomic percent of carbon of less than about 3.3% and an atomic percent of oxygen of less than about 1.0% and includes 4 or more barrier layers, each having a thickness of about 40 angstroms. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the stack has a resistivity of about 183 microhm-centimeter. 
     
     
         5 . The semiconductor device of  claim 1 , wherein each of the FeRAM capacitors and associated transistor forms a bit and a total population of the bits has a polarization in micro coulombs/cm 2  associated therewith and wherein a bit with the lowest data “1” value has a polarization that is within 40% of the data “1” peak polarization.