High bandwidth memory interface

Abstract

This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

1 . A memory module comprising:
 a plurality of bidirectional bus lines;   a plurality of synchronous memory devices having bidirectional data terminals; and   a buffer connected between the bus lines and the bidirectional data terminals of the plurality of synchronous memory devices, the buffer configured to capture and regenerate signals received on the bus lines for receipt by the plurality of synchronous memory devices, or to capture and regenerate signals received from any one of the plurality of synchronous memory devices onto the bus lines.   
     
     
         2 . The memory module as claimed in  claim 1  further comprising:
 a plurality of command lines, and each of the plurality of synchronous memory devices includes command terminals, and   a command buffer connected between the command lines and the command terminals, the command buffer configured to capture and regenerate command signals received on the command lines for provision to the command terminals.   
     
     
         3 . The memory module as claimed in  claim 2 , further including a clock input terminal, and the command buffer receives a clock signal from the clock input terminal for capturing the command signals received from the command lines. 
     
     
         4 . The memory module as claimed in  claim 3 , wherein the command buffer includes latches for capturing the command signals received from the command lines. 
     
     
         5 . The memory module as claimed in  claim 3 , wherein each of the plurality of synchronous memory devices includes a clock terminal, and the command buffer captures and regenerates the clock signal received from the clock input terminal for receipt by the clock terminal on each of the plurality of synchronous memory devices. 
     
     
         6 . The memory module as claimed in  claim 2 , wherein the memory module provides a wider data bus width than any single one of the synchronous memory devices 
     
     
         7 . The memory module as claimed in  claim 1 , wherein the bus lines includes a clock line carrying a source synchronous data clock signal. 
     
     
         8 . The memory module as claimed in  claim 7 , wherein the clock line is a bidirectional source synchronous data clock line. 
     
     
         9 . The memory module as claimed in  claim 1 , wherein the memory module provides a deeper address space than a single one of the synchronous memory devices. 
     
     
         10 . The memory module as claimed in  claim 1 , wherein the synchronous memory devices are double data rate (DDR) synchronous memory devices. 
     
     
         11 . The memory module as claimed in  claim 1 , wherein the synchronous memory devices are Dynamic Random Access Memory (DRAM) devices. 
     
     
         12 . The memory module as claimed in  claim 1 , wherein each of the synchronous memory devices includes on die termination resistors coupled to the bidirectional data terminals.