Semiconductor Wafer Processing to Increase the Usable Planar Surface Area

Abstract

The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.

1 - 25 . (canceled) 
     
     
         26 . A process for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to the substantially planar surface, the process comprising the steps of:
 a) selecting a strip thickness and a slot width for division of the wafer into a plurality of adjoining strips such that the thickness of the wafer is greater than the sum of the strip thickness and the slot width,   b) selecting a technique for forming a plurality of slots each slot having the slot width, and thereby forming the plurality of adjoining strips in the wafer with each strip having the strip thickness, wherein each of the slots when formed extend from the substantially planar surface at an angle thereto and the slots extending partly through the thickness of the wafer over either all of the slot length or most of the slot length; and   c) processing a portion of the wafer into the plurality of adjoining strips using the selected technique wherein the adjoining strips are supported within a frame.   
     
     
         27 . A process as claimed in  claim 26  wherein the slots extend 68% or more through the thickness of the wafer. 
     
     
         28 . A process as claimed in  claim 26  wherein the slots extend between 68% of the thickness of the wafer to all the way through the thickness of the wafer. 
     
     
         29 . A process as claimed in  claim 26  wherein the slots extend from between 68% to 76% of the thickness of the wafer to all the way through the thickness of the wafer. 
     
     
         30 . A process according to  claim 26  wherein the wafer comprises opposing front and rear surfaces, the front surface being the substantially planar surface, and wherein the slots extend from the front surface to within 160 micrometers or less from the rear surface of the wafer. 
     
     
         31 . A process as claimed in  claim 26  wherein the wafer comprises opposing front and rear surfaces, the front surface being the substantially planar surface, and wherein the slots extend from the front surface to within 50 micrometers or less from the rear surface of the wafer. 
     
     
         32 . A process as claimed in  claim 31  wherein the thickness of the wafer is about 500 micrometers. 
     
     
         33 . A process as claimed in  claim 26  wherein step (c) comprises processing a portion of the wafer into the plurality of adjoining strips using the selected technique wherein the adjoining strips are supported within a frame, the frame comprising an unprocessed portion of the wafer extending around the periphery of the wafer. 
     
     
         34 . A process according to  claim 26  wherein step (c) comprises processing a portion of the wafer into the plurality of adjoining strips using the selected technique to form a plurality of elongated slots extending all the way through the wafer over most of the slot length such that the adjoining strips are connected by at least one interconnecting portion spaced apart along the length of the adjoining strips. 
     
     
         35 . A process according to  claim 34  wherein the interconnecting portions are formed such that they connect adjoining strips to maintain a substantially constant gap between the strips and limit the amount of bending of the strips. 
     
     
         36 . A process as claimed in  claim 26  wherein the selected technique for processing a portion of the wafer into the plurality of adjoining strips is selected from the group of: photo electro-chemical etching; plasma etching; mechanical grinding; cutting the wafer using a dicing saw; laser cutting; or wet anisotropic etching. 
     
     
         37 . A process as claimed in  claim 26  wherein the selected technique for processing a portion of the wafer into the plurality of adjoining strips is laser cutting and comprises laser cutting from one or more sides of the wafer. 
     
     
         38 . A process as claimed in  claim 37  wherein the selected technique for processing a portion of the wafer into the plurality of adjoining strips involves use of an anisotropic etchant wherein the wafer is etched with a process comprising the steps of:
 i) inserting the wafer into the etchant so as to expose a plurality of groove areas in the surface of the wafer to the alkaline solution whilst another area on the surface of the wafer is not so exposed, whereby the plurality of groove areas is etched by the solution; and   ii) removing the wafer from the etchant so as to allow the alkaline solution to drain from the grooves formed by the etching of the groove areas; and   iii) repeating steps (i) and (ii) such that the repeated etching of the plurality of groove areas forms the plurality of slots in the wafer.   
     
     
         39 . A process as claimed in  claim 38  wherein the wafer is a (110) oriented semiconductor wafer and step (iii) comprises repeating steps (i) and (ii) such that the repeated etching of the plurality of groove areas forms the plurality of slots in the wafer to expose the (111) faces of the wafer. 
     
     
         40 . A process as claimed in  claim 26  wherein the process is a process for increasing the useable surface area of a polycrystalline silicon or single crystal silicon semiconductor wafer. 
     
     
         41 . A process as claimed in  claim 26  wherein step (c) comprises processing a portion of the wafer into the plurality of adjoining strips by forming a plurality of parallel slots using the selected technique wherein the adjoining strips are supported within a frame. 
     
     
         42 . A process as claimed in  claim 26  wherein the frame comprises an uncut area of the semiconductor wafer. 
     
     
         43 . A process as claimed in  claim 26  further comprising the step of separating the adjoining strips from the frame to form a plurality of separated strips. 
     
     
         44 . A process as claimed in  claim 43  wherein the process is a process for increasing the useable surface area of a semiconductor wafer by forming a plurality of strips from the wafer wherein the effective surface area of the plurality of separated strips is greater than the surface area of the wafer, thereby increasing the usable surface area of the wafer. 
     
     
         45 . A process as claimed in  claim 43  wherein the process is a process for increasing the useable surface area of a semiconductor wafer by forming a plurality of strips from the wafer wherein the effective surface area of the plurality of separated strips is at least 10 times the surface area of the wafer. 
     
     
         46 . A process as claimed in  claim 26  further comprising the step of texturing the surfaces of the strips exposed by the step of forming the slots. 
     
     
         47 . A process as claimed in  claim 26  wherein the thickness of each strip is selected to be between 50 and 250 micrometers. 
     
     
         48 . A process as claimed in  claim 26  wherein the thickness of each strip is selected to be less than 100 micrometers. 
     
     
         49 . A process as claimed in  claim 26  wherein the thickness of the wafer is selected to be between 200 and 1000 micrometers. 
     
     
         50 . A process as claimed in  claim 26  wherein the thickness of the wafer is selected to be at least 500 micrometers. 
     
     
         51 . A process according to  claim 26  wherein each of the slots when formed extend from the substantially planar surface at an angle thereto of about 90 degrees. 
     
     
         52 . A process according to  claim 26  wherein step (c) comprises processing a portion of the wafer into the plurality of adjoining strips by forming plurality of slots partially through the wafer using the selected technique, wherein the adjoining strips are supported within a frame. 
     
     
         53 . A process according to  claim 26  wherein the process further comprises the step of heavily doping one or more surfaces of the semiconductor wafer. 
     
     
         54 . A process as claimed in  claim 26  wherein in step (b) the technique is selected for forming a plurality of elongated slots extending nearly through the wafer. 
     
     
         55 . A process as claimed in  claim 26  wherein the technique is selected for forming a plurality of elongated slots formed through the wafer such that the slots extend all the way through the wafer over most of their length. 
     
     
         56 . A process as claimed in  claim 26  wherein the elongated slots are formed through the wafer such that the slots extend all the way through the wafer over most of their length. 
     
     
         57 . A process as claimed in  claim 26  wherein the length of the slot is much greater than the depth of the slot. 
     
     
         58 . A process as claimed in  claim 26  wherein the combined width of said slots and width between said slots is less than the depth of said slots. 
     
     
         59 . A process according to  claim 26  wherein the process further comprises the step of doping one or more surfaces of the semiconductor wafer prior to forming the plurality of slots. 
     
     
         60 . A process according to  claim 26  wherein each of the adjoining strips are defined by at most two slots. 
     
     
         61 . A process according to  claim 26  wherein the slots extend all the way through the wafer over either all of the slot length or most of the slot length. 
     
     
         62 . A process according to  claim 26  further comprising doping the surfaces of the strips exposed by forming the slots. 
     
     
         63 . A process according to  claim 62  further comprising forming the slots all the way through the wafer. 
     
     
         64 . A process according to  claim 62  further comprising separating the strips. 
     
     
         65 . A process according to  claim 26  wherein the slots are formed partly through the wafer, the process further comprising forming the slots all the way through the wafer and separating the strips to form a plurality of separated strips. 
     
     
         66 . A process for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to the substantially planar surface, the process comprising the steps of:
 a) selecting a strip thickness and a slot width for division of the wafer into a plurality of adjoining strips such that the thickness of the wafer is greater than the sum of the strip thickness and the slot width,   b) selecting a technique for forming a plurality of slots each slot having the slot width, and thereby forming the plurality of adjoining strips in the wafer with each strip having the strip thickness, wherein each of the slots when formed extend from the substantially planar surface at an angle thereto and the slots extending partly through the wafer over either all of the slot length of most of the slot length; and   c) processing a portion of the wafer into the plurality of adjoining strips using the selected technique wherein the adjoining strips are connected by multiple interconnecting portions.   
     
     
         67 . A process according to  claim 66  wherein portions of the slots extend all the way through the wafer, and the remaining portions of the slots extend partly through the wafer to form the interconnecting portions. 
     
     
         68 . A process according to  claim 66  wherein the interconnecting portions connect adjoining strips to maintain a substantially constant gap between the strips and limit the amount of bending of the strips. 
     
     
         69 . A process according to  claim 66  wherein the adjoining strips are supported within a frame comprised of an unprocessed portion around the periphery of the wafer. 
     
     
         70 . A process according to  claim 66  wherein the technique for forming at least part of the wafer into the adjoining strips is selected from the group of: photo electro-chemical etching; plasma etching; mechanical grinding; cutting the wafer using a dicing saw; laser cutting; or wet anisotropic etching. 
     
     
         71 . A process as claimed in  claim 66  wherein the slots are formed through the wafer such that the slots extend all the way through the wafer over most of their length. 
     
     
         72 . A process as claimed in  claim 66  wherein in step (b) the technique is selected for forming a plurality of elongated slots extending nearly through the wafer. 
     
     
         73 . A process as claimed in  claim 66  wherein the technique is selected for forming a plurality of parallel elongated slots formed through the wafer such that the slots extend all the way through the wafer over most of their length. 
     
     
         74 . A process according to  claim 66  wherein each of the adjoining strips are defined by at most two slots. 
     
     
         75 . A process according to  claim 66  wherein the slots extend through 70% or more of the thickness of the wafer. 
     
     
         76 . A process as claimed in  claim 66  wherein the slots extend between 70% of the thickness of the wafer to all the way through the thickness of the wafer. 
     
     
         77 . A process according to  claim 66  wherein the slots extend to approximately 160 micrometers or less from the rear surface of the wafer. 
     
     
         78 . A process according to  claim 66  wherein the slots extend to approximately 50 micrometers or less from the rear surface of the wafer. 
     
     
         79 . A process according to  claim 78  wherein the thickness of the wafer is about 500 micrometers. 
     
     
         80 . A process according to  claim 66  wherein the slots extend all the way through the wafer. 
     
     
         81 . A process according to  claim 66  further comprising doping the surfaces of the strips exposed by forming the slots. 
     
     
         82 . A process according to  claim 66  wherein the slots are formed partly through the wafer, the process further comprising forming the slots all the way through the wafer and separating the strips to form a plurality of separated strips. 
     
     
         83 . A process according to  claim 81  wherein the slots are formed partly through the wafer, the process further comprising forming the slots all the way through the wafer and separating the strips to form a plurality of separated strips.