Semiconductor device and a method of increasing a resistance value of an electric fuse

Abstract

Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

1 . A semiconductor device, comprising:
 a first insulator layer;
 a first trench formed in the first insulator layer; 
 a second trench formed in the first insulator layer; 
 an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench, and a first copper metal formed on the first barrier metal and filling in the first trench, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse; 
 a first wiring which includes a second barrier metal formed on a bottom surface of the second trench and a side wall of the second trench, and a second copper metal formed on the second barrier metal and filling in the second trench; 
 a second insulator layer formed on the first insulator layer, the electric fuse, and the first copper wiring; 
 a third insulator layer formed on the second insulator layer; 
 a third trench formed in the third insulator layer; 
 a second wiring which is formed in the third trench; 
 a fourth insulator layer formed over the third insulator layer; 
 a fourth trench formed in the fourth insulator layer; and 
 a third wiring which is formed in the fourth trench; 
 wherein a first thickness of the first wiring is thinner than a third thickness of the third wiring, and a second thickness of the second wiring is thinner than the third thickness of the third wiring; and 
 wherein a dielectric relative constant of the first and third insulator layer is 3 or less. 
   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
 wherein gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.   
     
     
         3 . The semiconductor device according to  claim 2 , further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse turning into a predetermined value or more. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the first thickness of the first wiring is thinner than the second thickness of the second wiring. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein a linear expansion coefficient of each of the first and second copper metals is higher than that of the first and third insulator layers, and
 wherein each of the first, second copper metals has lower melting point than melting point of each of the first and third insulator layers.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein the second insulator layer comprises two insulator films. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the second insulator layer comprises a SiCN film, a SiN film, or a bi-layered structure film having a SiCN film and a SiCO film. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein the second insulator layer includes a first compound film of silicon with nitride and a second compound film of silicon with oxide. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein the first compound film is comprised of SiCN, and the second compound film is comprised of SiCO. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the first barrier metal comprises:
 a first metal film which contacts with the first insulator layer at the side wall of the first trench, and is formed along the side wall of the first trench; and   a second metal film which contacts with the first metal film at the side wall of the first trench, the first insulator layer at the bottom surface of the first trench, and the first copper metal, and is formed along the side wall and the bottom surface of the first trench.   
     
     
         11 . The semiconductor device according to  claim 1 , wherein the first barrier metal has a higher melting point than a melting point of each of the first and second copper metals. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein a linear expansion coefficient of the first barrier metal is smaller than that of each of the first and second copper metals and is larger than that of the first and third insulator layers. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers. 
     
     
         14 . A semiconductor device, comprising:
 a semiconductor substrate;   a gate electrode formed over the semiconductor substrate;   an interlayer dielectric covering the gate electrode;   a fine layer formed over the interlayer dielectric;   a semiglobal layer formed over the fine layer;   a global layer formed over the semiglobal layer; and   an electric fuse formed in the fine layer, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse, the electric fuse including a copper metal,   wherein the electric fuse is formed in a trench of a first insulator layer of the fine layer, a second insulator layer is formed on the electric fuse and the first insulator layer, and a third insulator layer is formed on the third insulator layer,   wherein a dielectric relative constant of the first and third insulator layer is 3 or less,
 wherein a thickness of the semiglobal layer is thicker than that of the fine layer, and 
 wherein a thickness of the global layer is thicker than that of the semiglobal layer. 
   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the fine layers are plural,
 wherein the copper metal has a larger linear expansion coefficient than that of the first insulator layer, and further has a lower melting point than that of the first insulator layer.   
     
     
         16 . A semiconductor device, comprising:
 a first insulator layer;
 a first trench formed in the first insulator layer; 
 a second trench formed in the first insulator layer; 
 an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench and a first copper metal formed on the first barrier metal and filling in the first trench, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse; 
 a first wiring which includes a second barrier metal formed on a bottom surface of the second trench and a side wall of the second trench and a second copper metal formed on the second barrier metal and filling in the second trench; 
 a first layer which includes a second insulator layer formed on the first insulator layer, a third insulator layer formed on the second insulator layer, and a second wiring formed in the third insulator layer; and 
 a second layer which includes a fourth insulator layer formed over the third insulator layer and a third wiring formed over the third insulator layer; 
 wherein a first thickness of the first insulator layer is thinner than a third thickness of the second layer, and a second thickness of the first layer is thinner than the third thickness of the second layer; and 
 wherein a dielectric relative constant of the first and third insulator layer is 3 or less. 
   
     
     
         17 . The semiconductor device according to  claim 16 , further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
 wherein gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.   
     
     
         18 . The semiconductor device according to  claim 17 , further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse turning into a predetermined value or more. 
     
     
         19 . The semiconductor device according to  claim 16 , wherein the first thickness of the first insulator layer is thinner than the second thickness of the first layer. 
     
     
         20 . The semiconductor device according to  claim 16 , wherein a linear expansion coefficient of each of the first and second copper metals is higher than that of the first and third insulator layers, and
 wherein each of the first, second copper metals has a lower melting point than a melting point of each of the first and third insulator layers.   
     
     
         21 . The semiconductor device according to  claim 16 , wherein the second insulator layer comprises two insulator films. 
     
     
         22 . The semiconductor device according to  claim 16 , wherein the second insulator layer comprises a SiCN film, a SiN film, or a bi-layered structure film having a SiCN film and a SiCO film. 
     
     
         23 . The semiconductor device according to  claim 21 , wherein the second insulator layer includes a first compound film of silicon with nitride and a second compound film of silicon with oxide. 
     
     
         24 . The semiconductor device according to  claim 23 , wherein the first compound film is comprised of SiCN, and the second compound film is comprised of SiCO. 
     
     
         25 . The semiconductor device according to  claim 16 , wherein the first barrier metal comprises:
 a first metal film which contacts with the first insulator layer at the side wall of the first trench, and is formed along the side wall of the first trench; and   a second metal film which contacts with the first metal film at the side wall of the first trench, the first insulator layer at the bottom surface of the first trench, and the first copper metal, and is formed along the side wall and the bottom surface of the first trench.   
     
     
         26 . The semiconductor device according to  claim 16 , wherein the first barrier metal has a higher melting point than a melting point of each of the first and second copper metals. 
     
     
         27 . The semiconductor device according to  claim 26 , wherein a linear expansion coefficient of the first barrier metal is smaller than that of each of the first and second copper metals and is larger than that of the first and third insulator layers. 
     
     
         28 . The semiconductor device according to  claim 26 , wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers. 
     
     
         29 . A semiconductor device, comprising:
 a semiconductor substrate;   a gate electrode formed over the semiconductor substrate;
 a first insulator layer formed over the gate electrode and the semiconductor substrate; 
 a first trench formed in the first insulator layer; 
 an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench, and a copper metal formed on the first barrier metal and filling in the first trench, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse; 
 a second insulator layer formed on the first insulator layer and the electric fuse; and 
 a third insulator layer formed on the second insulator layer, 
 wherein a dielectric relative constant of the first and third insulator layer is 3 or less. 
   
     
     
         30 . The semiconductor device according to  claim 29 , further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
 wherein gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.   
     
     
         31 . The semiconductor device according to  claim 30 , further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse turning into a predetermined value or more. 
     
     
         32 . The semiconductor device according to  claim 29 , wherein a linear expansion coefficient of the copper metal is higher than that of the first and third insulator layers, and
 wherein the copper metal has a lower melting point than a melting point of each of the first and third insulator layers.   
     
     
         33 . The semiconductor device according to  claim 29 , wherein the second insulator layer includes two insulator films. 
     
     
         34 . The semiconductor device according to  claim 29 , wherein the second insulator layer comprises a SiCN film, a SiN film, or a bi-layered structure film having a SiCN film and a SiCO film. 
     
     
         35 . The semiconductor device according to  claim 33 , wherein the second insulator layer includes a first compound film of silicon with nitride and a second compound film of silicon with oxide. 
     
     
         36 . The semiconductor device according to  claim 35 , wherein the first compound film is comprised of SiCN, and the second compound film is comprised of SiCO. 
     
     
         37 . The semiconductor device according to  claim 29 , wherein the first barrier metal comprises:
 a first metal film which contacts with the first insulator layer at the side wall of the first trench, and is formed along the side wall of the first trench; and   a second metal film which contacts with the first metal film at the side wall of the first trench, the first insulator layer at the bottom surface of the first trench, and the copper metal, and is formed along the side wall and the bottom surface of the first trench.   
     
     
         38 . The semiconductor device according to  claim 29 , wherein the first barrier metal has a higher melting point than a melting point of the copper metal. 
     
     
         39 . The semiconductor device according to  claim 38 , wherein a linear expansion coefficient of the first barrier metal is smaller than that of the copper metal and is larger than that of the first and third insulator layers. 
     
     
         40 . The semiconductor device according to  claim 38 , wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers.