Row of floating point accumulators coupled to respective pes in uppermost row of pe array for performing addition operation

Abstract

Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

1 . A parallel processor for supporting a floating-point operation, comprising:
 a Processing Element (PE) array having a plurality of PEs; and   a floating-point accumulator array having accumulators respectively connected to PEs of one row in the PE array to accelerate a floating-point addition operation,   wherein the respective PEs of the PE array comprise a flag for floating-point multiplication used for normalization of floating-point multiplication.   
     
     
         2 . The parallel processor of  claim 1 , wherein the floating-point accumulator array includes the same number of accumulators as PEs included in an uppermost row of the PE array, and each of the accumulators communicates with a PE of the same column in the uppermost row.