Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.

1 .- 14 . (canceled) 
     
     
         15 . A nonvolatile semiconductor memory device fabrication method comprising:
 forming a first dielectric layer on a major surface of a semiconductor substrate;   forming a floating gate electrode layer on the first dielectric layer;   etching two side surfaces in a gate length direction of each of the floating gate electrode layer and the first dielectric layer;   covering, with an dielectric film, the two side surfaces in the gate length direction of the first dielectric layer and at least portions of the two side surfaces in the gate length direction of the floating gate electrode layer, thereby forming a buried dielectric layer having an upper surface positioned between an upper surface and a bottom surface of the floating gate electrode layer;   forming a second dielectric layer on the floating gate electrode layer and the buried dielectric layer, comprising:
 forming a lower dielectric film mainly containing silicon and nitrogen; 
 forming an intermediate dielectric film on the lower dielectric film; and 
 forming an upper dielectric film mainly containing silicon and nitrogen on the intermediate dielectric film; 
   forming a control gate electrode layer on the second dielectric layer;   etching two side surfaces in a gate width direction of each of the first dielectric layer, the floating gate electrode layer, the second dielectric layer, and the control gate electrode layer; and   forming, by oxidation, a first silicon oxide film is an interface between the floating gate electrode layer and the lower dielectric film.   
     
     
         16 . A method according to  claim 15 , wherein a corner of the floating gate electrode layer, which is formed along the gate width direction and in contact with the first silicon oxide film is rounded. 
     
     
         17 . A method according to  claim 15 , wherein the intermediate dielectric film is a silicon oxide film. 
     
     
         18 . A method according to  claim 15 , wherein forming the intermediate dielectric film comprises:
 forming a silicon oxide film;   forming an dielectric film mainly containing silicon and nitrogen on the silicon oxide film; and   forming another silicon oxide film on the dielectric film mainly containing silicon and nitrogen.   
     
     
         19 . A method according to  claim 15 , further comprising, before the oxidation, wet-etching the lower dielectric film to make a width in the gate length direction of the lower dielectric film smaller than a width in the gate length direction of the floating gate electrode layer. 
     
     
         20 . A method according to  claim 15 , wherein the oxidation is one of oxidation executed in one of a steam ambient and an oxygen ambient, and plasma oxidation. 
     
     
         21 . A nonvolatile semiconductor memory device fabrication method comprising:
 forming a first dielectric layer on a major surface of a semiconductor substrate;   forming a floating gate electrode layer on the first dielectric layer;   etching two side surfaces in a gate length direction of each of the floating gate electrode layer and the first dielectric layer;   covering, with an dielectric film, the two side surfaces in the gate length direction of the first dielectric layer and at least portions of the two side surfaces in the gate length direction of the floating gate electrode layer, thereby forming a buried dielectric layer having an upper surface positioned between an upper surface and a bottom surface of the floating gate electrode layer;   forming a second dielectric layer on the floating gate electrode layer and the buried dielectric layer, the forming the second dielectric layer comprising:
 forming a lower dielectric film mainly containing silicon and nitrogen; 
 forming an intermediate dielectric film on the lower dielectric film; and 
 forming an upper dielectric film mainly containing silicon and nitrogen on the intermediate dielectric film; 
   forming a control gate electrode layer on the second dielectric layer;   etching two side surfaces in a gate width direction of each of the first dielectric layer, the floating gate electrode layer, the second dielectric layer, and the control gate electrode layer; and   forming, by oxidation, a first silicon oxide film in an interface between the control gate electrode layer and the upper dielectric film.   
     
     
         22 . A method according to  claim 21 , wherein a corner of the control gate electrode layer, which is formed along the gate width direction and in contact with the first silicon oxide film is rounded. 
     
     
         23 . A method according to  claim 21 , wherein the intermediate dielectric film is a silicon oxide film. 
     
     
         24 . A method according to  claim 21 , wherein forming the intermediate dielectric film comprises:
 forming a silicon oxide film;   forming an dielectric film mainly containing silicon and nitrogen on the silicon oxide film; and   forming another silicon oxide film on the dielectric film mainly containing silicon and nitrogen.   
     
     
         25 . A method according to  claim 21 , further comprising, before the oxidation, wet-etching the upper dielectric film to make a width in the gate length direction of the upper dielectric film smaller than a width in the gate length direction of the control gate electrode layer. 
     
     
         26 . A method according to  claim 21 , wherein the oxidation is one of oxidation executed in one of a steam ambient and an oxygen ambient, and plasma oxidation.