Thermal processing method

Abstract

A thermal processing method is provided. First, a semiconductor substrate is provided. The semiconductor substrate has a metal-oxide-semiconductor transistor formed thereon. The metal-oxide-semiconductor transistor includes a gate and source and drain regions on two sides of the gate. Dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the semiconductor substrate. Next, a first thermal process is performed, and then a second thermal process is performed. Next, the cap layer is removed. The thermal processing method is capable of uniformly heating a semiconductor substrate and reducing the pattern effect in the fabrication of a CMOS and to improve the performance of the CMOS.

1 . A thermal processing method, comprising:
 providing a semiconductor substrate having a metal-oxide-semiconductor transistor formed thereon, wherein the metal-oxide-semiconductor transistor comprises a gate and a source and drain region on two sides of the gate;   implanting dopants into the source and drain region and the gate;   forming a cap layer over the semiconductor substrate after the implanting step without any thermal treatment therebetween;   performing a first thermal process;   performing a second thermal process; and   removing the cap layer.   
     
     
         2 . The thermal processing method as claimed in  claim 1 , wherein the cap layer comprises an amorphous carbon layer. 
     
     
         3 . The thermal processing method as claimed in  claim 2 , wherein the cap layer is removed by a dry etching process followed by post etch cleaning process. 
     
     
         4 . The thermal processing method as claimed in  claim 1 , wherein the cap layer comprises a stress memorization technique layer. 
     
     
         5 . The thermal processing method as claimed in  claim 4 , wherein the stress memorization technique layer comprises a material selected from a group consisting of silicon nitride and silicon oxide. 
     
     
         6 . The thermal processing method as claimed in  claim 4 , wherein the cap layer is removed by a wet etching process. 
     
     
         7 . The thermal processing method as claimed in  claim 1 , wherein the step of forming the cap layer over the semiconductor substrate comprises the steps of: forming a stress memorization technique layer on the semiconductor substrate and forming an amorphous carbon layer on the stress memorization technique layer; and the step of removing the cap layer comprises the steps of: removing the amorphous carbon layer and removing the stress memorization technique layer from the semiconductor substrate. 
     
     
         8 . The thermal processing method as claimed in  claim 1 , wherein the first thermal process is a rapid thermal process, and the second thermal process is a millisecond annealing process. 
     
     
         9 . The thermal processing method as claimed in  claim 1 , wherein the first thermal process is a millisecond annealing process, and the second thermal process is a rapid thermal process. 
     
     
         10 . The thermal processing method as claimed in  claim 1 , wherein the first thermal process and the second thermal process are performed simultaneously. 
     
     
         11 . The thermal processing method as claimed in  claim 1 , wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, the rapid thermal process and millisecond annealing process are respectively applied onto the second surface and the first surface. 
     
     
         12 . The thermal processing method as claimed in  claim 1 , wherein the rapid thermal process and millisecond annealing process are respectively applied onto the first surface. 
     
     
         13 . The thermal processing method as claimed in  claim 1 , wherein an amorphorization step is performed before the cap layer is formed. 
     
     
         14 . A thermal processing method, comprising:
 providing a semiconductor substrate having a metal-oxide-semiconductor transistor formed thereon, wherein the metal-oxide-semiconductor transistor comprises a gate and source and drain regions on two sides of the gate;   implanting dopants into the source and drain region and the gate;   forming a cap layer over the semiconductor substrate after the implanting step without any thermal treatment therebetween;   performing a first thermal process;   removing the cap layer after performing the first thermal process; and   performing a second thermal process.   
     
     
         15 . The thermal processing method as claimed in  claim 14 , wherein the cap layer comprises a stress memorization technique layer. 
     
     
         16 . The thermal processing method as claimed in  claim 15 , wherein the stress memorization technique layer comprises a material selected from a group consisting of silicon nitride and silicon oxide. 
     
     
         17 . The thermal processing method as claimed in  claim 14 , wherein the first thermal process is a rapid thermal process, and the second thermal process is a millisecond annealing process. 
     
     
         18 . The thermal processing method as claimed in  claim 14 , wherein an amorphorization step is performed before the cap layer is formed. 
     
     
         19 . The thermal processing method as claimed in  claim 14 , wherein an amorphorization step is an implantation step.