Stack-type semiconductor device and method of manufacturing the same

Abstract

A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.

1 . A method for manufacturing a stack-type semiconductor device, comprising:
 stacking and mounting, on a circuit board with bonding pads, a first semiconductor chip with first electrode and a second semiconductor chip with second electrode pads; and   wire-bonding with wires the bonding pads, the first electrode pads and the second electrode pads as a whole.   
     
     
         2 . The manufacturing method as set forth in  claim 1 ,
 wherein one ends of the bonding wires are ball-bonded to the second electrode pads and other ends of the bonding wires are stitch-bonded to the bonding pads, and the intermediate portions of the bonding wires are stitch-bonded to stud bumps formed on the first electrode pads.   
     
     
         3 . The manufacturing method as set forth in  claim 1 ,
 wherein one ends of the bonding wires are ball-bonded to the bonding pads and other ends of the bonding wires are stitch-bonded to the second electrode pads, and the intermediate portions of the bonding wires are stitch-bonded to stud bumps formed on the first electrode pads.   
     
     
         4 . The manufacturing method as set forth in  claim 2 ,
 wherein other stud bumps are stacked on the corresponding stud bumps to which the bonding wires are stitched.   
     
     
         5 . The manufacturing method as set forth in  claim 2 ,
 wherein other stud bumps are stacked on the corresponding stud bumps to which the bonding wires are stitched.   
     
     
         6 . The manufacturing method as set forth in  claim 2 ,
 wherein the circuit board constitutes a lead frame, and the first semiconductor chip and the second semiconductor chip are stepwise stacked so that the edges of the semiconductor chips positioned in the same side are exposed, and the first electrode pads and the second electrode pads are formed in almost parallel on the exposed edges of the semiconductor chips, whereby the stack-type semiconductor device constitutes a TSOP (Thin Small Outline Package) structured semiconductor device.   
     
     
         7 . The manufacturing method as set forth in  claim 3 ,
 wherein the circuit board constitutes a lead frame, and the first semiconductor chip and the second semiconductor chip are stepwise stacked so that the edges of the semiconductor chips positioned in the same side are exposed, and the first electrode pads and the second electrode pads are formed in almost parallel on the exposed edges of the semiconductor chips, whereby the stack-type semiconductor device constitutes a TSOP (Thin Small Outline Package) structured semiconductor device.   
     
     
         8 . The manufacturing method as set forth in  claim 2 ,
 wherein the circuit board constitutes a lead frame, and the first semiconductor chip and the second semiconductor chip are stepwise stacked so that the edges of the semiconductor chips positioned in the same side are exposed, and the first electrode pads and the second electrode pads are formed in almost parallel on the exposed edges of the semiconductor chips, and at least one of the first semiconductor chip and the second semiconductor chip constitutes a memory chip so that the stack-type semiconductor device constitutes a NAND-type flash memory.   
     
     
         9 . The manufacturing method as set forth in  claim 3 ,
 wherein the circuit board constitutes a lead frame, and the first semiconductor chip and the second semiconductor chip are stepwise stacked so that the edges of the semiconductor chips positioned in the same side are exposed, and the first electrode pads and the second electrode pads are formed in almost parallel on the exposed edges of the semiconductor chips, and at least one of the first semiconductor chip and the second semiconductor chip constitutes a memory chip so that the stack-type semiconductor device constitutes a NAND-type flash memory.   
     
     
         10 . The manufacturing method as set forth in  claim 2 ,
 wherein the stud bumps are formed by pressing, on the first electrode pads, a ball portion formed at the forefront of a wire projecting from the inserting hole of a capillary.   
     
     
         11 . The manufacturing method as set forth in  claim 10 , wherein the stud bumps are formed under supersonic vibration while the ball portion is pressed on the first electrode pads. 
     
     
         12 . The manufacturing method as set forth in  claim 6 ,
 wherein the lead frame has a plurality of inner leads connected to the bonding pads   the inner leads including:   first inner circuit board leads and second inner circuit board leads under the condition that both ends of the first inner circuit board leads are extended in a first direction and the first and second inner circuit board leads are divided in a second direction orthogonal to the first direction so that forefronts of the second inner circuit board leads are arranged around a center in the second direction and forefronts of the first inner circuit board leads are arranged outside in the second direction.   
     
     
         13 . The manufacturing method as set forth in  claim 8 ,
 wherein the lead frame has a plurality of inner leads connected to the bonding pads   the inner leads including:   
       first inner circuit board leads and second inner circuit board leads under the condition that both ends of the first inner circuit board leads are extended in a first direction and the first and second inner circuit board leads are divided in a second direction orthogonal to the first direction so that forefronts of the second inner circuit board leads are arranged around a center in the second direction and forefronts of the first inner circuit board leads are arranged outside in the second direction.