Damage Implantation of a Cap Layer

Abstract

A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

1 . An integrated circuit comprising:
 a cap layer comprising silicon and nitrogen in contact with annealed source/drain regions and a gate electrode of a transistor;   wherein said cap layer contains an electrically neutral species.   
     
     
         2 . The integrated circuit of  claim 1  wherein said electrically neutral species comprises Ar. 
     
     
         3 . The integrated circuit of  claim 1  wherein said electrically neutral species comprises Sb. 
     
     
         4 . The integrated circuit of  claim 1  wherein said cap layer also contains another electrically neutral species. 
     
     
         5 . An integrated circuit comprising:
 a cap layer comprising silicon and carbon in contact with annealed source/drain regions and a gate electrode of a transistor;   wherein said cap layer contains an electrically neutral species.   
     
     
         6 . The integrated circuit of  claim 5  wherein said electrically neutral species comprises Ar. 
     
     
         7 . The integrated circuit of  claim 5  wherein said electrically neutral species comprises Sb. 
     
     
         8 . The integrated circuit of  claim 5  wherein said cap layer also contains another electrically neutral species. 
     
     
         9 . An integrated circuit comprising:
 a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor; and   a cap layer comprising silicon and nitrogen in contact with said silicon oxide liner film;   wherein said cap layer contains an electrically neutral species.   
     
     
         10 . The integrated circuit of  claim 9  wherein said electrically neutral species comprises Ar. 
     
     
         11 . The integrated circuit of  claim 9  wherein said electrically neutral species comprises Sb. 
     
     
         12 . The integrated circuit of  claim 9  wherein said cap layer also contains another electrically neutral species. 
     
     
         13 . An integrated circuit comprising:
 a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor; and   a cap layer comprising silicon and carbon in contact with said silicon oxide liner film;   wherein said cap layer contains an electrically neutral species.   
     
     
         14 . The integrated circuit of  claim 13  wherein said electrically neutral species comprises Ar. 
     
     
         15 . The integrated circuit of  claim 13  wherein said electrically neutral species comprises Sb. 
     
     
         16 . The integrated circuit of  claim 13  wherein said cap layer also contains another electrically neutral species. 
     
     
         17 . An integrated circuit comprising:
 a cap layer comprising silicon and nitrogen in contact with unannealed source/drain regions and a gate electrode of a transistor;   wherein said cap layer contains an electrically neutral species.   
     
     
         18 . The integrated circuit of  claim 17  wherein said electrically neutral species comprises Ar. 
     
     
         19 . An integrated circuit comprising:
 a cap layer comprising silicon and carbon in contact with unannealed source/drain regions and a gate electrode of a transistor;   wherein said cap layer contains an electrically neutral species.   
     
     
         20 . The integrated circuit of  claim 19  wherein said electrically neutral species comprises Ar.