Processor and method for executing load operation and store operation thereof

Abstract

A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.

1 . A method for executing a store operation, comprising:
 providing a store buffer;   when executing a store operation, adding a new entry in the store buffer according to the store operation if the store buffer has no entry which has a same address as an address of the store operation; and   merging data of the store operation into an existing entry of the store buffer if the address of the store operation is the same as an address of the existing entry.   
     
     
         2 . The method for executing the store operation according to  claim 1 , wherein the new entry includes the address, a mask and the data of the store operation. 
     
     
         3 . The method for executing the store operation according to  claim 1 , wherein merging the data of the store operation into the existing entry includes:
 generating a mask of the store operation according to the address and a data type of the store operation;   generating a merged mask according to the mask of the store operation and a mask of the existing entry;   generating merged data according to the mask and data of the store operation and data of the existing entry; and   storing the merged mask and the merged data into the existing entry.   
     
     
         4 . The method for executing the store operation according to  claim 3 , wherein the merged mask is generated based on a logic operation on the mask of the store operation and the mask of the existing entry; each bit of the mask of the store operation is a first preset value or a second preset value, a portion of the merged data that corresponds to the first preset value adopts the data of the store operation, and a portion of the merged data that corresponds to the second preset value adopts the data of the existing entry. 
     
     
         5 . The method for executing the store operation according to  claim 1 , further comprising:
 providing a data cache; and   writing data of an entry having a longest history in the store buffer into the data cache if no read/write competition occurs in the data cache.   
     
     
         6 . A method for executing a load operation, comprising:
 providing a data cache and a store buffer;   when executing a load operation, reading data required by the load operation from the data cache if there is no memory dependency between all entries of the store buffer and the load operation, the memory dependency being such that an address of any of the entries is the same as an address of the load operation and a mask of said entry overlaps with a mask of the load operation;   providing complete data required by the load operation by an existing entry of the store buffer if there is memory dependency between the existing entry and the load operation and the existing entry contains the complete data required by the load operation; and   generating the complete data required by the load operation according to data of the existing entry of the store buffer and data of a corresponding entry of the data cache if there is memory dependency between the existing entry and the load operation and the existing entry does not contain the complete data.   
     
     
         7 . The method for executing the load operation according to  claim 6 , wherein an address of the existing entry is the same as an address of the corresponding entry. 
     
     
         8 . The method for executing the load operation according to  claim 6 , wherein the complete data is generated based on a mask and the data of the existing entry and the data of the corresponding entry. 
     
     
         9 . The method for executing the load operation according to  claim 8 , wherein each bit of the mask of the existing entry is a first preset value or a second preset value, a portion of the complete data that corresponds to the first preset value adopts the data of the existing entry, and a portion of the complete data that corresponds to the second preset value adopts the data of the corresponding entry. 
     
     
         10 . A processor comprising:
 a data cache configured to store data read from a memory; and   a store buffer coupled to the data cache and configured for temporary storage of an address and data of a store operation when a load operation and the store operation compete to access the data cache; wherein   the processor adds a new entry in the store buffer according to the store operation if the store buffer has no entry which has a same address as the address of the store operation; and   the processor merges the data of the store operation into an existing entry of the store buffer if the address of the store operation is the same as an address of the existing entry.   
     
     
         11 . The processor according to  claim 10 , wherein the new entry includes the address, a mask and the data of the store operation. 
     
     
         12 . The processor according to  claim 10 , wherein when merging the data of the store operation into the existing entry, the processor generates a mask of the store operation according to the address and a data type of the store operation, generates a merged mask according to the mask of the store operation and a mask of the existing entry, generates merged data according to the mask and the data of the store operation and data of the existing entry, and stores the merged mask and the merged data into the existing entry. 
     
     
         13 . The processor according to  claim 12 , wherein the merged mask is generated based on a logic operation on the mask of the store operation and the mask of the existing entry; each bit of the mask of the store operation is a first preset value or a second preset value, a portion of the merged data that corresponds to the first preset value adopts the data of the store operation, and a portion of the merged data that corresponds to the second preset value adopts the data of the existing entry. 
     
     
         14 . The processor according to  claim 10 , wherein the processor writes data of an entry having a longest history in the store buffer into the data cache if no read/write competition occurs in the data cache. 
     
     
         15 . A processor comprising:
 a data cache configured to store data read from a memory; and   a store buffer coupled to the data cache and configured for temporary storage of an address and data of a store operation when a load operation and the store operation compete to access the data cache; wherein   the processor reads data required by the load operation from the data cache if there is no memory dependency between all entries of the store buffer and the load operation, the memory dependency being such that an address of any of the entries is the same as an address of the load operation and a mask of said entry overlaps with a mask of the load operation;   the processor reads complete data required by the load operation from an existing entry of the store buffer if there is memory dependency between the existing entry and the load operation and the existing entry contains the complete data required by the load operation; and   the processor generates the complete data required by the load operation according to data of the existing entry of the store buffer and data of a corresponding entry of the data cache if there is memory dependency between the existing entry and the load operation and the existing entry does not contain the complete data.   
     
     
         16 . The processor according to  claim 15 , wherein an address of the existing entry is the same as an address of the corresponding entry. 
     
     
         17 . The processor according to  claim 15 , wherein the complete data is generated based on a mask and the data of the existing entry and the data of the corresponding entry. 
     
     
         18 . The processor according to  claim 17 , wherein each bit of the mask of the existing entry is a first preset value or a second preset value, a portion of the complete data that corresponds to the first preset value adopts the data of the existing entry, and a portion of the complete data that corresponds to the second preset value adopts the data of the corresponding entry.