Clock recovery from data streams containing embedded reference clock values

Abstract

A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

1 . (canceled) 
   
   
       2 . A digitally implemented clock recovery apparatus for clock recovery from a data stream containing embedded reference clock values, the apparatus comprising:
 a clock reference register operable to store clock reference values received from the incoming data stream;   a digital comparator operable to compare the stored clock reference values and a locally generated clock reference values, and to provide a control value in response; and   a controlled clock source operable to provide a locally generated clock signal synchronized with the clock reference values in response to the control value, wherein the controlled clock source includes a controllable digital fractional divider operable to receive the control value and a clock input from a digital clock synthesizer.   
   
   
       3 . The apparatus of  claim 2 , wherein the digital clock synthesizer is driven by a fixed oscillator. 
   
   
       4 . The apparatus of  claim 2 , further including a local clock reference register operable to store the locally generated clock reference values. 
   
   
       5 . The apparatus of  claim 2 , further including a counter operable to receive the locally generated clock signal and provide the locally generated clock reference values. 
   
   
       6 . The apparatus of  claim 2 , wherein the gain of the comparator is adjusted in accordance with changing input conditions. 
   
   
       7 . The apparatus of  claim 6 , wherein the gain of the comparator is adjusted to a high value prior to obtaining a match between the controlled clock source and the clock reference and reduced after obtaining the match. 
   
   
       8 . The apparatus of  claim 2 , wherein the data stream comprises an MPEG data stream. 
   
   
       9 - 14 . (canceled) 
   
   
       14 . An improved apparatus for clock recovery from data streams containing embedded reference clock values comprising:
 clock reference storage means for storing clock reference values received from the incoming data stream connected to, input of a digital comparator means, the second input of which is connected to,   local clock (LC) storage means for storing locally generated clock values provided by a,   a counter which receives a clock signal from a controllable digital fractional divider controlled by the output of said digital comparator,   wherein said controllable digital fractional divider receives a control value from said digital comparator and a clock input from a digital clock synthesizer means driven by a fixed oscillator.   
   
   
       15 . An improved apparatus as claimed in  claim 14 , wherein said input data stream is an MPEG data stream in which said embedded clock reference value is either the program clock reference (PCR) value or elementary stream clock reference (ESCR) value. 
   
   
       16 . An improved apparatus as claimed in  claim 14 , wherein said digital comparator means is implemented using a microcontroller. 
   
   
       17 .- 25 . (canceled)