Non-volatile Memory Device

Abstract

This patent relates to a non-volatile memory device and a driving method thereof. The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line.

1 . A non-volatile memory device comprising:
 one or more source select transistors each of which has a gate including first and second conductive layers isolated from each other;   one or more drain select transistors each of which has a gate including first and second conductive layers isolated from each other; and   a plurality of memory cells in which a floating gate and a control gate are isolated from each other,   wherein the plurality of memory cells are connected between the source select transistors and the drain select transistors.   
   
   
       2 . The non-volatile memory device of  claim 1 , wherein the source select transistors comprise two source select transistors. 
   
   
       3 . The non-volatile memory device of  claim 1 , wherein the drain select transistors comprise two drain select transistors. 
   
   
       4 . A non-volatile memory device comprising:
 one or more source select transistors each of which has a gate including first and second conductive layers isolated from each other;   a single drain select transistor which has a gate including first and second conductive layers isolated from each other; and   a plurality of memory cells in which a floating gate and a control gate are isolated from each other,   wherein the plurality of memory cells are connected between the source select transistors and the drain select transistor.   
   
   
       5 . The non-volatile memory device of  claim 4 , wherein the source select transistors comprise two source select transistors. 
   
   
       6 . A non-volatile memory device comprising:
 a single source select transistor which has a gate including first and second conductive layers isolated from each other;   one or more drain select transistors each of which has a gate including first and second conductive layers isolated from each other; and   a plurality of memory cells in which a floating gate and a control gate are isolated from each other,   wherein the plurality of memory cells are connected between the source select transistor and the drain select transistors.   
   
   
       7 . The non-volatile memory device of  claim 6 , wherein the drain select transistors comprise two drain select transistors. 
   
   
       8 . A non-volatile memory device comprising:
 a plurality of strings each of which is coupled between a bit line and a common source line, each string including a plurality of memory cells coupled between a source select transistor being connected to the common source line and a drain select transistor being connected to the bit line, each of the source select transistor and the drain select transistor comprising:   a tunnel oxide film firmed on a semiconductor substrate;   a first conductive layer formed on the tunnel oxide film;   a dielectric layer formed on the entire first conductive layer; and   a second conductive layer formed on the dielectric film.