test structure and probe for differential signals

Abstract

A test structure including a differential gain cell and a differential signal probe include compensation for the Miller effect reducing the frequency dependent variability of the input impedance of the test structure.

1 . A test structure comprising a cell including a first input signal probe pad capacitively interconnected to a first output signal probe pad and a second input signal probe pad capacitively interconnected to a second output signal probe pad, said test structure comprising:
 (a) a first capacitor interconnecting said first input signal probe pad and said second output signal probe pad; and   (b) a second capacitor interconnecting said second input signal probe pad and said first output signal probe pad, wherein said first capacitor has a capacitance related to a capacitance of said interconnection of said first input signal probe pad and said first output signal probe pad and said second capacitor has a capacitance related to a capacitance of said interconnection of said second input signal probe pad and said second output signal probe pad.   
     
     
         2 . The test structure of  claim 1  wherein said first capacitor has a capacitance substantially equal to a capacitance of said interconnection of said first input signal probe pad and said first output signal probe pad and said second capacitor has a capacitance substantially equal to a capacitance of said interconnection of said second input signal probe pad and said second output signal probe pad. 
     
     
         3 . A probe for probing a cell comprising a first input signal probe pad capacitively interconnected to a first output signal probe pad and a second input signal probe pad capacitively interconnect to a second output signal probe pad, said probe comprising:
 (a) a first probe tip connectible to a source of a first input signal and arranged for contact with said first input signal probe pad of said cell;   (b) a second probe tip connectible to a source of a second input signal and arranged for contact with said second input signal probe pad;   (c) a third probe tip connectible to a sink of a first output signal and arranged for contact with said first output signal probe pad;   (d) a fourth probe tip connectible to a sink of a second output signal and arranged to contact said second output signal probe pad;   (e) a first capacitive structure interconnecting said first probe tip and said fourth probe tip; and   (f) a second capacitive structure interconnecting said second probe tip and said third probe tip.   
     
     
         4 . The probe of  claim 3  wherein said first, said second, said third and said fourth probe tips are arranged in a linear array. 
     
     
         5 . The probe of  claim 3  wherein said capacitive structure interconnecting said first probe tip and said fourth probe tip has a capacitance substantially equal to a capacitance of said interconnection of said first input signal probe pad and said first output signal probe pad and said capacitive structure interconnecting said second probe tip and said third probe tip has a capacitance substantially equal to a capacitance of said interconnection of said second input signal probe pad and said second output signal probe pad. 
     
     
         6 . The probe of  claim 5  wherein said first, said second, said third and said fourth probe tips are arranged in a linear array. 
     
     
         7 . A method for probing a cell comprising a first input signal probe pad capacitively interconnected to a first output signal probe pad and a second input signal probe pad capacitively interconnected to a second output signal probe pad, said method comprising steps of:
 (a) interconnecting said first input signal probe pad and said second output signal probe pad with a capacitor approximately equaling a capacitance of said interconnection of said first input signal probe pad and said first output signal probe pad; and   (b) interconnecting said second input signal probe pad and said first output probe pad with a capacitor approximately equaling a capacitance of said interconnection of said second input signal probe pad and said second output signal probe pad.   
     
     
         8 . A test structure for testing a functionality of a transistor, said test structure comprising:
 (a) a first transistor including:
 (i) a first terminal connectible through a first resistance to a source of a first component of a signal; 
 (ii) a second terminal connectible through a second resistance to a sink for a first component of an output signal and interconnected to said first terminal by a parasitic capacitance; and 
 (iii) a third terminal; 
   (b) a second transistor including:
 (i) a first terminal connectible through a third resistance to a source of a second component of a signal; 
 (ii) a second terminal connectible through a fourth resistance to a sink for a second component of an output signal and interconnected to said first terminal by a parasitic capacitance; and 
 (iii) a third terminal interconnected with said third terminal of said first transistor and a source of a bias voltage; 
   (c) a first compensating capacitive structure connecting said first terminal of said first transistor to said second terminal of said second transistor; and   (d) a second compensating capacitive structure connecting said first terminal of said second transistor to said second terminal of said first transistor.   
     
     
         9 . The test structure of  claim 8  wherein said first compensating capacitive structure has a capacitance substantially equal to said parasitic capacitance interconnecting said first terminal of said first transistor and said second terminal of said first transistor and said second compensating capacitive structure has a capacitance substantially equal to said parasitic capacitance interconnecting said first terminal of said second transistor to said second terminal of said second transistor. 
     
     
         10 . The test structure of  claim 8  wherein said first, said second, said third and said fourth resistances have values selected to cause said test structure to have a gain approximating unity.