Semiconductor varactor with reduced parasitic resistance

Abstract

A semiconductor varactor with reduced parasitic resistance is disclosed. A contact isolation structure ( 32 ) is formed in a well region ( 20 ). The gate contact structures ( 70 ) are formed above the contact isolation structure ( 32 ) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer ( 50 ) over the well regions ( 20 ) in a further embodiment to reduce the parasitic resistance.

1 . An integrated circuit including a varactor, comprising:
 a semiconductor substrate with at least a first isolation region and a second isolation region separated by a first distance;   a well region of a first conductivity type formed in said semiconductor substrate between said first isolation region and said second isolation region;   at least a first and a second active region defined in said well region by a contact isolation structure formed in said well region between said first isolation region and said second isolation region;   contact regions of the first conductivity type formed in the first and second active regions;   a gate dielectric layer formed on said first active region and said second active region;   a gate electrode layer formed on said gate dielectric layer, wherein said gate electrode layer overlies said first active region, said second active region, and said contact isolation structure; and   electrical contacts to said gate electrode layer, wherein said electrical contacts are formed over said contact isolation region.   
   
   
       2 . The integrated circuit of  claim 1 , wherein said first and second isolation regions comprise shallow trench isolation (STI) structures. 
   
   
       3 . The integrated circuit of  claim 1 , wherein said contact isolation structure comprises a shallow trench isolation (STI) structure. 
   
   
       4 . An integrated circuit including a varactor, comprising
 a well region of a first conductivity type formed in a semiconductor;   a gate dielectric layer formed on said well region;   a gate electrode layer formed on said gate dielectric layer;   contact regions of the first conductivity type formed in said well region, wherein said contact regions are source/drain implantations; and   electrical contacts to said gate electrode layer, wherein said electrical contacts overlie a contact isolation structure formed in said well region.   
   
   
       5 . The integrated circuit of  claim 4 , further comprising sidewall structures formed adjacent to said gate electrode layer. 
   
   
       6 . The integrated circuit of  claim 5 , wherein said first conductivity type is n-type conductivity. 
   
   
       7 . The integrated circuit of  claim 6 , wherein said first conductivity type is p-type conductivity. 
   
   
       8 . The integrated circuit of  claim 4 , wherein said contact isolation structure comprises a shallow trench isolation (STI) structure.