Bandgap engineered mos-gated power transistors

Abstract

Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate.

1 . An MOS-gated transistor, comprising:
 a trench;   a body region adjacent to the trench;   a source region adjacent to the trench and forming a first pn junction with the body region;   a drain region adjacent to the trench and forming a second pn junction with the body region;   a channel region vertically extending along a side wall of the trench and being adjacent to at least a portion of the body region, and   a gate region extending in the trench between the source region and the drain region, the gate region including a polycrystalline semiconductor material having a resistivity lower than that of a polycrystalline silicon and lower than that of a single crystalline silicon.   
     
     
         2 . The transistor of  claim 1 , further comprising a source contact that contact the source region and does not contact the body region. 
     
     
         3 . The transistor of  claim 1 , wherein the gate region comprises polysilicon germanium. 
     
     
         4 . The transistor of  claim 1 , wherein the gate region comprises silicon-germanium (SiGe). 
     
     
         5 . The transistor of  claim 4 , wherein the gate region comprises a silicon-germanium (SiGe) material without a metal silicide. 
     
     
         6 . The transistor of  claim 4 , wherein the gate region comprises a silicon-germanium (SiGe) region in direct contact with a gate dielectric. 
     
     
         7 . The transistor of  claim 4 , wherein the gate region comprises Si 1-x  Ge x  where 0.1<x<0.8. 
     
     
         8 . The transistor of  claim 4 , wherein the germanium concentration is between 10 and 30 percent mole fraction. 
     
     
         9 . The MOS-gated transistor of  claim 1 , wherein:
 the MOS-gated transistor is a p-type trench MOS-gate transistor having a p-type SiGe trench gate;   a source terminal of the p-type MOS-gated transistor is coupled to an input of a driver circuit;   a drain terminal of the p-type MOS-gated transistor is coupled to an output of the driver circuit;   the drain terminal of the p-type MOS-gated transistor is coupled to a drain terminal of an n-type MOS-gated trench transistor; and   a source terminal of the n-type MOS-gated trench transistor is coupled to a ground terminal.   
     
     
         10 . An MOS-gated transistor, comprising:
 a first trench and a second trench separated by a mesa region;   a body region in the mesa region and adjacent to the first and the second trenches;   a first source region adjacent to the first trench and forming a first pn junction with the body region;   a second source region adjacent to the second trench and forming a second pn junction with the body region;   a drain region adjacent to the first and the second trenches and forming a third pn junction with the body region;   a first channel region vertically extending along a side wall of the first trench and being adjacent to at least a first portion of the body region;   a second channel region vertically extending along a side wall of the second trench and being adjacent to at least a second portion of the body region;   a first gate region extending in the first trench between the first source region and the drain region, the first gate region including a polycrystalline semiconductor material having a resistivity lower than that of a polycrystalline silicon and lower than that of a single crystalline silicon; and   a conductive material in contact with the first source region, the second source region, and a third portion of the body region between the first and the second source regions.   
     
     
         11 . The transistor of  claim 10 , wherein the gate region comprises polysilicon germanium. 
     
     
         12 . The transistor of  claim 10 , wherein the gate region comprises silicon-germanium (SiGe). 
     
     
         13 . The transistor of  claim 12 , wherein the gate region comprises Si 1-x  Ge x  where 0.1<x<0.8. 
     
     
         14 . The transistor of  claim 10 , wherein the gate region comprises a silicon-germanium (SiGe) region in direct contact with a gate dielectric. 
     
     
         15 . A driver circuit, comprising:
 a p-type trench MOS-gate transistor having a p-type SiGe trench gate;   a source terminal of the p-type trench MOS-gated transistor coupled to an input of the driver circuit;   a drain terminal of the p-type trench MOS-gated transistor coupled to an output of the driver circuit;   an n-type MOS-gated trench transistor, a drain terminal of the n-type MOS-gated transistor being coupled to the drain terminal of the p-type MOS-gated transistor; and   a source terminal of the n-type MOS-gated trench transistor coupled to a ground terminal.   
     
     
         16 . The driver circuit of  claim 15 , wherein the p-type SiGe trench gate comprises Si 1-x  Ge x  where 0.1<x<0.8. 
     
     
         17 . The driver circuit of  claim 15 , wherein the p-type SiGe trench gate comprises Si 1-x  Ge x  where 0.1<x<0.3. 
     
     
         18 . The driver circuit of  claim 15 , wherein p-type SiGe trench gate is a polycrystalline semiconductor material having a resistivity lower than that of a polycrystalline silicon and lower than that of a single crystalline silicon. 
     
     
         19 . The driver circuit of  claim 15 , wherein p-type SiGe trench gate comprises a silicon-germanium (SiGe) region in direct contact with a gate dielectric. 
     
     
         20 . The driver circuit of  claim 15 , further comprising a control signal coupled to a gate terminal of the p-type trench MOS-gate transistor.