Display panel and method of forming thereof

Abstract

A panel a gate line on a first substrate, a gate insulating layer covering the gate line, a semiconductor layer on the gate insulating layer, a data line intersecting the gate line and including a source electrode and a drain electrode facing the source electrode on the semiconductor layer, a connection assistant separated from the data line, a passivation layer covering the semiconductor layer and including contact holes exposing the connection assistant and a pixel electrode including a plurality of sub-pixel electrodes and formed on the passivation layer. The sub-pixel electrodes are connected to the connection assistant through the contact holes, are electrically connected to each other through the connection assistant and at least one of the sub-pixel electrodes is electrically connected to the drain electrode.

1 .- 20 . (canceled) 
   
   
       21 . A panel, comprising:
 a first substrate;   a gate line formed on the first substrate;   a data line intersecting the gate line;   a thin film transistor connected to the gate line and the data line; and   a pixel electrode connected to the thin film transistor and including a plurality of sub-pixel electrodes and connection assistants connecting the sub-pixel electrodes to each other,   wherein the connection assistants are disposed on the left side or the right side of the pixel.   
   
   
       22 . The panel of  claim 21 , further comprising:
 a second substrate facing the first substrate;   a light blocking member formed on the second substrate; and   a common electrode formed on the second substrate,   wherein the connection assistants overlap the light blocking member.   
   
   
       23 . The panel of  claim 22 , wherein the sub-pixel electrodes have a substantially rectangular shape with rounded corners and the connection assistants are connected to left edges or right edges of the sub-pixel electrodes. 
   
   
       24 . The panel of  claim 23 , wherein the connection assistants are alternately connected to left and right edges of the sub-pixel electrodes. 
   
   
       25 . The panel of  claim 24 , wherein the common electrode includes a plurality of cutouts. 
   
   
       26 . The panel of  claim 25 , wherein the cutouts have a circular shape. 
   
   
       27 . The panel of  claim 21 , wherein the connection assistants are connected to facing edges of adjacent sub-pixel electrodes. 
   
   
       28 . The panel of  claim 21 , wherein the sub-pixel electrodes include a transmission electrode. 
   
   
       29 . The panel of  claim 21 , wherein at least one of the sub-pixel electrodes includes a reflection electrode. 
   
   
       30 . The panel of  claim 21 , wherein the connection assistants are formed in a same layer as the pixel electrode. 
   
   
       31 . The panel of  claim 21 , wherein the connection assistants connect the sub pixel electrode to each other. 
   
   
       32 . A panel, comprising:
 a first substrate;   a gate line formed on the first substrate;   a data line intersecting the gate line;   a thin film transistor connected to the gate line and the data line;   a pixel electrode connected to the thin film transistor and including a plurality of sub-pixel electrodes; and   a connection assistant separated from the data line and connecting the sub-pixel electrodes to each other.   
   
   
       33 . The panel of  claim 32 , wherein the connection assistant is disposed on a same layer as the pixel electrode. 
   
   
       34 . The panel of  claim 33 , wherein the connection assistant is formed in the same layer as the pixel electrode. 
   
   
       35 . The panel of  claim 32 , further comprising:
 a second substrate facing the first substrate;   a light blocking member formed on the second substrate; and   a common electrode formed on the second substrate,   wherein the connection assistant overlaps the light blocking member.   
   
   
       36 . The panel of  claim 35 , wherein the sub-pixel electrodes have a substantially rectangular shape with rounded corners and the connection assistant is connected to left edges or right edges of the sub-pixel electrodes. 
   
   
       37 . The panel of  claim 36 , wherein the connection assistant is alternately connected to left and right edges of the sub-pixel electrodes. 
   
   
       38 . The panel of  claim 35 , wherein the common electrode includes a plurality of cutouts. 
   
   
       39 . The panel of  claim 38 , wherein the cutouts have a circular shape. 
   
   
       40 . The panel of  claim 32 , wherein the connection assistant is connected to facing edges of adjacent sub-pixel electrodes.