Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage

Abstract

First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

1 . A method for forming a single-level electrically erasable and programmable read only memory, the method comprising:
 providing a semiconductor substrate having a first well and a second well;   defining and forming a plurality of isolation regions in the semiconductor substrate, and simultaneously, a first device region is formed in the first well, a second device region is formed adjacent said first well, a third device region is formed between said second well and said second device region and a fourth device region is formed in said second well;   forming a first dielectric layer having a first thickness on said semiconductor substrate;   performing an ion-implanting process to form a control gate in said second device region under said first dielectric layer;   removing said partial first dielectric layer located on said semiconductor substrate of said first well and said second well;   forming a second dielectric layer having a second thickness on said partial semiconductor substrate located on said first well and said second well;   removing said partial second dielectric layer located on said fourth device region;   forming a third dielectric layer having a third thickness on said first device region, said second device region and said fourth device region, wherein said third dielectric layer and said second dielectric layer are stacked from each other to form a fourth dielectric layer having a fourth thickness on said first device region; and further, said third dielectric layer and said first dielectric layer are stacked from each other to form a fifth dielectric layer having a fifth thickness on said second device region; and   forming and defining a plurality of gates on these dielectric layers of said first device region, said second device region, said third device region and said fourth device region, wherein there is the same gate located on said first device region and said second device region, which serves as the floating gate.   
     
     
         2 . The method according to  claim 1 , wherein said first dielectric layer is a high-voltage dielectric layer. 
     
     
         3 . The method according to  claim 1 , wherein said second thickness is about less than said first thickness. 
     
     
         4 . The method according to  claim 1 , wherein said third dielectric layer is a low-voltage dielectric layer. 
     
     
         5 . The method according to  claim 1 , wherein said third thickness is about less than the second thickness. 
     
     
         6 . The method according to  claim 1 , wherein said fifth thickness of said fifth dielectric layer on said second device region is more than said first thickness of said first dielectric layer on said third device region; and further, said first thickness of said first dielectric layer on said third device region is more than said fourth thickness of said fourth dielectric layer on said first device region; and further, said fourth thickness of said fourth dielectric layer on said first device region is more than said third thickness of said third dielectric layer on said fourth device region. 
     
     
         7 . The method according to  claim 1 , wherein the first part of said floating gate is located on the dielectric layer of said first device region and the second part of said floating gate is located on the dielectric layer of said second device region. 
     
     
         8 . The method according to  claim 1 , wherein said third device region can be operated in the opposite electric field about 18V. 
     
     
         9 . The method according to  claim 8 , wherein the opposite electric field comprises the range of −6V to 12V, −12V to 6V and −9V to 9V. 
     
     
         10 . A method for forming a single-level electrically erasable and programmable read only memory, the method comprising:
 providing a semiconductor substrate having a first conductivity;   forming a first deep well and a second deep well in said semiconductor substrate, wherein said first deep well and said second deep well have a second conductivity;   forming a plurality of isolating regions and wells in said semiconductor substrate, wherein a first well having said first conductivity is formed in said first deep well, a second well having said second conductivity is formed in the adjacent region beside said first deep well, a third well having said first conductivity is formed in the adjacent region beside said second deep well, a fourth well having said second conductivity is formed in the adjacent region between said second deep well and said third well, a fifth well having said first conductivity and a sixth well having said second conductivity are formed in said second deep well;   forming a first dielectric layer having a first thickness on said semiconductor substrate;   forming a depletion layer in said second well to reduce the resistances;   removing said partial first dielectric layer located on said semiconductor substrate of said first deep well and said second deep well;   forming a second dielectric layer having a second thickness on said partial semiconductor substrate located on said first well and said second well;   removing said partial second dielectric layer located on the second deep well;   forming a third dielectric layer having a third thickness on said first deep well, said second well and said second deep well, wherein said third dielectric layer and said second dielectric layer are stacked from each other to form a fourth dielectric layer having a fourth thickness on said first deep well, said third dielectric layer and said first dielectric layer are stacked from each other to form a fifth dielectric layer having a fifth thickness on said second well;   forming and defining a plurality of gates on these dielectric layers of said first well, said second well, said third well, said fourth well, said fifth well and said sixth well, wherein there is the same gate located on said first well and said second well, which serves as a floating gate, and the first part of said floating gate is located on said fourth dielectric layer of said first well and the second part of said floating gate is located on said fifth dielectric layer of said second well;   forming a first doped region having said second conductivity in said third well and a second doped region having a first conductivity in said fourth well, individually;   forming a third doped region having said second conductivity in said first well under the first part of said floating gate to define the source region of said floating gate located under one side of the first part of the floating gate;   forming a fourth doped region having said second conductive in said fifth well and a fifth doped region having said first conductive in said sixth well;   first heavy doping said second doped region in said fourth well and said fifth doped region in said sixth well; and   second heavy doping said third doped region in said first well and said depletion layer in said second well, said first doped region in said third well and said fourth doped region in said fifth well, and a sixth doped region is formed in said first well under the first part of said floating gate to define the drain region of said floating gate under the other side of the first part of said floating gate, and a seventh doped region is formed in said depletion layer located under one side of the second part of said floating gate to serve as the control gate.   
     
     
         11 . The method according to  claim 10 , wherein said first conductivity comprises P-type dopant, and said second conductivity comprises N-type dopant. 
     
     
         12 . The method according to  claim 10 , wherein said first well and said second well are an EEPROM device region, said third well and said fourth well are a high-voltage device region, said fifth well and said sixth well are a low-voltage device region. 
     
     
         13 . The method according to  claim 12 , wherein said high-voltage device region can be operated in the opposite electric field about 18V. 
     
     
         14 . The method according to  claim 13 , wherein the opposite electric field comprises the range of −6V to 12V, −12V to 6V and −9V to 9V. 
     
     
         15 . The method according to  claim 10 , wherein said plurality of isolating regions comprises field-oxide layer. 
     
     
         16 . The method according to  claim 10 , wherein said first thickness is about 200 Å to 600 Å. 
     
     
         17 . The method according to  claim 10 , wherein said depletion layer is a doped region having said second conductivity. 
     
     
         18 . The method according to  claim 10 , wherein said second thickness is about 60 Å to 80 Å. 
     
     
         19 . The method according to  claim 10 , wherein said third thickness is about 50 Å to 70 Å. 
     
     
         20 . The method according to  claim 10 , wherein said fifth thickness of said fifth dielectric layer is more than said first thickness of said first dielectric layer; and further, said first thickness of said first dielectric layer is more than said fourth thickness of said fourth dielectric layer; and further, said fourth thickness of said fourth dielectric layer is more than said third thickness of said third dielectric layer. 
     
     
         21 . A method for forming a single-level electrically erasable and programmable read only memory, comprising:
 providing a semiconductor substrate having a first well and a second well;   defining and forming a plurality of isolation regions in or on the semiconductor substrate, wherein a first device region is thus formed in the first well, a second device region is formed adjacent the first well, at least one third device region is formed between the second device region and the second well, and at least one fourth device region is formed in the second well;   forming a first dielectric layer having a first thickness, a second dielectric layer having a second thickness, and a third dielectric layer having a third thickness, in such a way that the second dielectric layer and the third dielectric layer are stacked on the semiconductor substrate within the first device region, the first dielectric layer and the third dielectric layer are stacked on the semiconductor substrate within the second device region, the first dielectric layer is on the semiconductor substrate within said at least one third device region, and the third dielectric layer is on the semiconductor substrate within said at least one fourth device region;   forming a doped region in the semiconductor substrate within the second device region; and   forming a first floating gate on the semiconductor substrate within the first device region, and a second floating fate on the semiconductor substrate within the second device region.