Structure and Method for Thin Single or Multichip Semiconductor QFN Packages

Abstract

A semiconductor device has one or more semiconductor chips with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments separated from the chip by gaps; the segments have first and second surfaces, wherein the second surfaces are coplanar with the passive chip surface. Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces.

1 . A semiconductor device comprising:
 a flat bottom surface;   a semiconductor chip having an active surface and a passive surface;   a plurality of metal segments surrounding the chip, each segment having a top and a bottom surface;   a gap between the chip and the metal segments filled with a polymeric compound;   the flat bottom surface including the bottom surfaces of the metal segments, the passive surface of the semiconductor chip, and the polymeric compound; and   the bottom surfaces of the metal segments having a ground texture.   
     
     
         2 . The semiconductor device of  claim 1 , in which the passive surface of the semiconductor chip has a surface texture similar to the ground texture on the bottom surfaces of the metal segments. 
     
     
         3 . The semiconductor device of  claim 2 , in which the polymeric compound on the bottom surface of the semiconductor device has a surface texture similar to the ground texture on the bottom surfaces of the metal segments. 
     
     
         4 . The semiconductor of  claim 1 , in which the metal segments have sidewall surfaces with a surface texture of an etched surface. 
     
     
         5 . The semiconductor of  claim 4 , in which the sidewall surfaces terminate at the bottom surface of the semiconductor device. 
     
     
         6 . The semiconductor of  claim 1 , further comprising bond wires bridging the gap connecting the metal segments and the active surface of the semiconductor chip.