Semiconductor device

Abstract

A semiconductor device including: a base substrate; a frame body mounted on the base substrate and formed with a recessed portion in each of both side faces thereof opposing to each other; a semiconductor chip mounted on the base substrate within an area of the frame body; a dielectric block inserted into the recessed portion in the frame body; a waveguide formed on a surface of the dielectric block and electrically connected with the semiconductor chip; a plurality of protection patterns respectively formed along the waveguide at positions spaced from the waveguide on both sides of the waveguide on the surface of the dielectric block; and a metal layer formed on at least each of the both side faces of the dielectric block opposing to each other by plating.

1 . A semiconductor device comprising:
 a base substrate;   a frame body mounted on the base substrate and formed with a recessed portion in each of both side faces thereof opposing to each other;   a semiconductor chip mounted on the base substrate within an area of the frame body;   a dielectric block inserted into the recessed portion in the frame body;   a waveguide formed on a surface of the dielectric block and electrically connected with the semiconductor chip;   a plurality of protection patterns respectively formed along the waveguide at positions spaced from the waveguide on both sides of the waveguide on the surface of the dielectric block; and   a metal layer formed on at least each of the both side faces of the dielectric block opposing to each other by plating.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the metal layer includes a first metal layer formed on at least each of both side faces of the dielectric block opposing to each other by plating and a second metal layer produced on the protection pattern as a result of formation of the first metal layer. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein a protection wall is formed on each of surfaces of the plurality of protection patterns. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein the protection wall is formed at a position nearest to the waveguide, on the surfaces of the plurality of protection patterns. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein each of the plurality of protection patterns is formed to be in contact with two sides not bordering on the waveguide, of four sides constituting the surface of the dielectric block. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein each of the plurality of protection patterns is formed to be in contact with a part of the two sides. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein each of the plurality of protection patterns is formed at a position spaced from the two sides. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein each of the plurality of protection patterns is formed to always have a substantially equal distance relative to the waveguide. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein each of the plurality of protection patterns is formed to have a substantially equal width. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein each of the plurality of protection patterns is formed from the same material as that of the waveguide. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the dielectric block is composed of a first dielectric block formed with the waveguide and the plurality of protection patterns and a second dielectric block formed on the first dielectric block. 
     
     
         12 . The semiconductor device according to  claim 1 , wherein a lid is placed on the frame body. 
     
     
         13 . The semiconductor device according to  claim 1 , wherein the semiconductor chip is a GaAs-based field effect transistor. 
     
     
         14 . The semiconductor device according to  claim 1 , wherein,
 on the base substrate within the frame body, there are mounted a dielectric substrate and a circuit pattern formed on the dielectric substrate and connected with the semiconductor chip through a first connection portion,   the waveguide is connected with the circuit pattern through a second connection portion, and   the waveguide is electrically connected with the semiconductor chip through the first connection portion, the circuit pattern and the second connection portion.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the circuit pattern is a matching circuit. 
     
     
         16 . The semiconductor device according to  claim 1 , wherein the waveguide is a microstrip line. 
     
     
         17 . The semiconductor device according to  claim 1 , wherein the metal layer is formed from gold. 
     
     
         18 . The semiconductor device according to  claim 14 , wherein the first connection portion is comprised of a plurality of wires. 
     
     
         19 . The semiconductor device according to  claim 18 , wherein each of wires is formed from gold. 
     
     
         20 . The semiconductor device according to  claim 14 , wherein the second connection portion is comprised of a plurality of wires. 
     
     
         21 . The semiconductor device according to  claim 20 , wherein each of wires is formed from gold. 
     
     
         22 . The semiconductor device according to  claim 14 , wherein the first connection portion is formed from metal foil. 
     
     
         23 . The semiconductor device according to  claim 22 , wherein the metal foil is formed from gold. 
     
     
         24 . The semiconductor device according to  claim 14 , wherein the second connection portion is formed from metal foil. 
     
     
         25 . The semiconductor device according to  claim 24 , wherein the metal foil is formed from gold.