Semiconductor device and method for fabricating the same

Abstract

It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.

1 . A semiconductor device comprising:
 a gate insulating layer formed over a semiconductor layer;   wherein the semiconductor layer has a channel formation region, a source region, a drain region, and an impurity region formed between the channel formation region and the source region; wherein the channel formation region and the drain region are provided in contact with each other;   a gate electrode layer formed over the channel formation region and the impurity region via the gate insulating layer; and   a silicide formed on the surface of the source region and the drain region.   
     
     
         2 . A semiconductor device comprising:
 a gate insulating layer formed over a semiconductor layer;   wherein the semiconductor layer has a channel formation region, a source region, a drain region, and an impurity region formed between the channel formation region and the drain region; wherein the channel formation region and the source region are provided in contact with each other;   a gate electrode layer formed over the channel formation region and the impurity region via the gate insulating layer; and   a silicide formed on the surface of the source region and the drain region.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the impurity region has an impurity element for imparting a p-type, and the source region and the drain region have an impurity element for imparting an n-type. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the impurity region has an impurity element for imparting an n-type, and the source region and the drain region have an impurity element for imparting a p-type. 
     
     
         5 . A semiconductor device comprising:
 a gate insulating layer over a semiconductor layer;   wherein the semiconductor layer has a channel formation region, a source region, a drain region, a first impurity region formed between the channel formation region and the source region, a second impurity region formed between the source region and the first impurity region, and a third impurity region formed between the drain region and the channel formation region;   wherein the channel formation region and the third impurity region are provided in contact with each other;   a gate electrode layer formed over the channel formation region and the first impurity region via the gate insulating layer; and   a silicide formed on the surface of the source region and the drain region,   wherein the second impurity region, the third impurity region, the source region, and the drain region have an impurity element for imparting one conductive type, and wherein the concentration of the element for imparting one conductive type in the second impurity region and the third impurity region is lower than that of the impurity element for imparting one conductive type in the source region and the drain region.   
     
     
         6 . A semiconductor device comprising:
 a gate insulating layer over a semiconductor layer;   wherein the semiconductor layer has a channel formation region, a source region, a drain region, a first impurity region formed between the channel formation region and the drain region, a second impurity region formed between the source region and the channel formation region, and a third impurity region formed between the drain region and the first impurity region;   wherein the channel formation region and the second impurity region are provided in contact with each other;   a gate electrode layer formed over the channel formation region and the first impurity region via the gate insulating layer; and   a silicide formed on the surface of the source region and the drain region,   wherein the second impurity region, the third impurity region, the source region, and the drain region have an impurity element for imparting one conductive type, and wherein the concentration of the impurity element for imparting one conductive type in the second impurity region and the third impurity region is lower than that of the impurity element for imparting one conductive type in the source region and the drain region.   
     
     
         7 . The semiconductor device according to  claim 5 , wherein the first impurity region has an impurity element for imparting a p-type, and the second impurity region, the third impurity region, the source region, and the drain region have an impurity element for imparting an n-type. 
     
     
         8 . The semiconductor device according to  claim 5 , wherein the first impurity region has an impurity element for imparting an n-type, and
 wherein the second impurity region, the third impurity region, the source region, and the drain region have an impurity element for imparting a p-type.   
     
     
         9 . The semiconductor device according to  claim 1 , wherein an insulating layer is formed on a side surface of the gate electrode layer. 
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein an insulating layer is formed over the semiconductor layer, the gate insulating layer, and the gate electrode layer,   wherein an opening is formed to reach the silicide in the insulating layer, and   wherein a source electrode layer and a drain electrode layer being in contact with the silicide are formed in the opening.   
     
     
         11 . A semiconductor device comprising:
 a gate insulating layer formed over a first semiconductor layer and a second semiconductor layer;   wherein the first semiconductor layer has a first channel formation region, a first source region, a first drain region, and a first impurity region formed between the first channel formation region and the first source region,   and the second semiconductor layer has a second channel formation region, a second source region, a second drain region, and a second impurity region formed between the second channel formation region and the second drain region;   wherein the first channel formation region and the first drain region are provided in contact with each other, and the second channel formation region and the second source region are provided in contact with each other,   a first gate electrode layer formed over the first channel formation region and the first impurity region via the gate insulating layer,   a second gate electrode layer formed over the second channel formation region and the second impurity region via the gate insulating layer, and   a silicide formed on the surface of the first source region, the second source region, the first drain region, and the second drain region.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein the first source region, the second source region, the first drain region, and the second drain region have an impurity element for imparting an n-type, and the first impurity region and the second impurity region have an impurity element for imparting a p-type. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein the first source region, the second source region, the first drain region, and the second drain region have an impurity element for imparting a p-type, and the first impurity region and the second impurity region have an impurity element for imparting an n-type. 
     
     
         14 . A method for manufacturing a semiconductor device comprising:
 forming an amorphous semiconductor film over an insulating surface;   forming a crystalline semiconductor film by emitting laser light to the amorphous semiconductor film;   forming a semiconductor layer by patterning the crystalline semiconductor film;   forming a gate insulating layer over the semiconductor layer;   forming a gate electrode layer over the gate insulating layer;   forming a first impurity region by doping an impurity element for imparting a first one conductive type to the semiconductor layer from one direction diagonally to the surface thereof using the gate electrode layer as a mask;   forming a second impurity region, a third impurity region, a fourth impurity region, and a channel formation region by doping an impurity element for imparting a second one conductive type to the semiconductor layer perpendicularly to the surface thereof using the gate electrode layer as a mask;   forming an insulating layer on a side surface of the gate electrode layer;   removing the gate insulating layer over the third impurity region and the fourth impurity region of the semiconductor layer using the gate electrode layer and the insulating layer as a mask;   forming a source region, a fifth impurity region to be in contact with the source region, a drain region, and a sixth impurity region to be in contact with the drain region by doping an impurity element for imparting a third one conductive type to the semiconductor layer perpendicularly to the surface thereof using the gate electrode layer and the insulating layer as a mask; and   forming a silicide in the source region and the drain region,   wherein each concentration of the impurity element for imparting the second one conductive type and the impurity element for imparting the third one conductive type in the fifth impurity region and the sixth impurity region is lower than that of the impurity element for imparting the second one conductive type and the impurity element for imparting the third one conductive type in the source region and the drain region,   the second impurity region is formed over the semiconductor layer covered with the gate electrode layer between the channel formation region and the fifth impurity region, and   the sixth impurity region is formed in contact with the channel formation region.   
     
     
         15 . A method for manufacturing a semiconductor device comprising:
 forming an amorphous semiconductor film over an insulating surface;   forming a crystalline semiconductor film by emitting laser light to the amorphous semiconductor film;   forming a semiconductor layer by patterning the crystalline semiconductor film;   forming a gate insulating layer over the semiconductor layer;   forming a gate electrode layer over the gate insulating layer;   forming a first impurity region by doping an impurity element for imparting a first one conductive type to the semiconductor layer from one direction diagonally to the surface thereof using the gate electrode layer as a mask;   forming a second impurity region, a third impurity region, a fourth impurity region, and a channel formation region by doping an impurity element for imparting a second one conductive type to the semiconductor layer perpendicularly to the surface thereof using the gate electrode layer as a mask;   forming an insulating layer on a side surface of the gate electrode layer;   removing the gate insulating layer over the third impurity region and the fourth impurity region in the semiconductor layer using the gate electrode layer and the insulating layer as a mask;   forming a source region, a fifth impurity region to be in contact with the source region, a drain region, and a sixth impurity region to be in contact with the drain region by doping an impurity element for imparting a third one conductive type to the semiconductor layer perpendicularly to the surface thereof using the gate electrode layer and the insulating layer as a mask; and   forming a silicide in the source region and the drain region,   wherein each concentration of the impurity element for imparting the second one conductive type and the impurity element for imparting the third one conductive type in the fifth impurity region and the sixth impurity region is lower than that of the impurity element for imparting the second one conductive type and the impurity element for imparting the third one conductive type in the source region and the drain region,   the second impurity region is formed in the semiconductor layer covered with the gate electrode layer between the channel formation region and the sixth impurity region, and   the fifth impurity region is formed in contact with the channel formation region.   
     
     
         16 . The method for manufacturing a semiconductor device according to  claim 14 ,
 wherein the first impurity region and the second impurity region are formed by doping an impurity element for imparting a p-type as the impurity element for imparting the first one conductive type, and   wherein the third impurity region, the fourth impurity region, the fifth impurity region, the sixth impurity region, the source region, and the drain region are formed by doping an impurity element for imparting an n-type as the impurity element for imparting the second one conductive type and the impurity element for imparting the third one conductive type.   
     
     
         17 . The method for manufacturing a semiconductor device according to  claim 14 ,
 wherein the first impurity region and the second impurity region are formed by doping an impurity element for imparting an n-type as the impurity element for imparting the first one conductive type, and   wherein the third impurity region, the fourth impurity region, the fifth impurity region, the sixth impurity region, the source region, and the drain region are formed by doping an impurity element for imparting a p-type as the impurity element for imparting the second one conductive type and the impurity element for imparting the third one conductive type.   
     
     
         18 . The method for manufacturing a semiconductor device according to  claim 14 ,
 wherein the first impurity region is formed by doping an impurity element for imparting a first one conductive type to the semiconductor layer from one direction in an incident angle θ 1  to the surface thereof, and   wherein the second impurity region, the third impurity region, the fourth impurity region, and the channel formation region are formed by doping an impurity element for imparting a second one conductive type to the semiconductor layer with an incident angle θ 2  to the surface thereof,   wherein an angular difference between the angle θ 1  and the angle θ 2  is set at 5° or more.   
     
     
         19 . The manufacturing method of a semiconductor device according to  claim 14 ,
 wherein an interlayer insulating layer is formed over the semiconductor layer, the silicide, and the gate electrode layer, an opening is formed to reach the silicide in the interlayer insulating layer, and a source electrode layer and a drain electrode layer being in contact with the silicide are formed in the opening.   
     
     
         20 . The method for manufacturing a semiconductor device according to  claim 14 , wherein the silicide is formed by heating a metal film formed over the semiconductor layer on the surface of the source region and the drain region. 
     
     
         21 . The method for manufacturing a semiconductor device according to  claim 14 , wherein the laser light is continuous wave laser light. 
     
     
         22 . The method for manufacturing a semiconductor device according to  claim 14 , wherein the laser light is pulsed laser light, and a pulse repetition frequency of the pulsed laser light is 0.5 MHz or more. 
     
     
         23 . The semiconductor device according to  claim 2 , wherein the impurity region has an impurity element for imparting a p-type, and the source region and the drain region have an impurity element for imparting an n-type. 
     
     
         24 . The semiconductor device according to  claim 2 , wherein the impurity region has an impurity element for imparting an n-type, and the source region and the drain region have an impurity element for imparting a p-type. 
     
     
         25 . The semiconductor device according to  claim 6 , wherein the first impurity region has an impurity element for imparting a p-type, and the second impurity region, the third impurity region, the source region, and the drain region have an impurity element for imparting an n-type. 
     
     
         26 . The semiconductor device according to  claim 6 , wherein the first impurity region has an impurity element for imparting an n-type, and the second impurity region, the third impurity region, the source region, and the drain region have an impurity element for imparting a p-type. 
     
     
         27 . The semiconductor device according to  claim 2 , wherein an insulating layer is formed on a side surface of the gate electrode layer. 
     
     
         28 . The semiconductor device according to  claim 5 , wherein an insulating layer is formed on a side surface of the gate electrode layer. 
     
     
         29 . The semiconductor device according to  claim 6 , wherein an insulating layer is formed on a side surface of the gate electrode layer. 
     
     
         30 . The semiconductor device according to  claim 2 , wherein an insulating layer is formed over the semiconductor layer, the gate insulating layer, and the gate electrode layer, an opening is formed in the insulating layer to reach the silicide, and a source electrode layer and a drain electrode layer are formed in the opening to reach the silicide. 
     
     
         31 . The semiconductor device according to  claim 5 , wherein an insulating layer is formed over the semiconductor layer, the gate insulating layer, and the gate electrode layer, an opening is formed in the insulating layer to reach the silicide, and a source electrode layer and a drain electrode layer are formed in the opening to reach the silicide. 
     
     
         32 . The semiconductor device according to  claim 6 , wherein an insulating layer is formed over the semiconductor layer, the gate insulating layer, and the gate electrode layer, an opening is formed in the insulating layer to reach the silicide, and wherein a source electrode layer and a drain electrode layer are formed in the opening to be in contact with the silicide. 
     
     
         33 . The method for manufacturing a semiconductor device according to  claim 15 ,
 wherein the first impurity region and the second impurity region are formed by adding an impurity element for imparting a p-type as the impurity element for imparting the first one conductive type, and   wherein the third impurity region, the fourth impurity region, the fifth impurity region, the sixth impurity region, the source region, and the drain region are formed by adding an impurity element for imparting an n-type as the impurity element for imparting the second one conductive type and the third one conductive type.   
     
     
         34 . The method for manufacturing a semiconductor device according to  claim 15 ,
 wherein the first impurity region and the second impurity region are formed by adding an impurity element for imparting an n-type as the impurity element for imparting the first conductive type, and   wherein the third impurity region, the fourth impurity region, the fifth impurity region, the sixth impurity region, the source region, and the drain region are formed by adding an impurity element for imparting a p-type as the impurity element for imparting the second one conductive type and the third one conductive type.   
     
     
         35 . The method for manufacturing a semiconductor device according to  claim 15 ,
 wherein the first impurity region is formed by doping the impurity element for imparting the first one conductive type to the semiconductor layer with at an incident angle θ 1  to the surface thereof, and   wherein the second impurity region, the third impurity region, the fourth region, and the channel formation region are formed by doping the impurity element for imparting the second one conductive type to the semiconductor layer at an incident angle θ 2  to the surface thereof,   wherein an angular difference between the angle θ 1  and the angle θ 2  is set at 5° or more.   
     
     
         36 . The method for manufacturing a semiconductor device according to  claim 15 ,
 wherein an interlayer insulating layer is formed over the semiconductor layer and the silicide and the gate electrode layer,   wherein an opening is formed in the interlayer insulating layer to reach the silicide, and   wherein a source electrode layer and a drain electrode layer are formed in the opening to reach the silicide.   
     
     
         37 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the silicide is formed by heating a metal film formed over the semiconductor layer on the surface of the source region and the drain region. 
     
     
         38 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the laser light is continuous-wave laser light. 
     
     
         39 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the laser light is pulsed laser light, and a pulse repetition frequency of the pulsed laser light is 0.5 MHz or more.