US2010237348A1PendingUtilityA1

Thin Film Transistor Array Substrate

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Assignee: AU OPTRONICS CORPPriority: Mar 19, 2009Filed: Jan 7, 2010Published: Sep 23, 2010
Est. expiryMar 19, 2029(~2.7 yrs left)· nominal 20-yr term from priority
Inventors:Chin-An TsengHung-Lung HouChia-Yu LeeChieh-Wei ChenKung-Ching ChuYen-Heng HuangChung-Kai ChenYi-Tsun LinChun-Jen Chiu
H10D 86/441H10D 86/60H10D 30/6729
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Claims

Abstract

A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode.

Claims

exact text as granted — not AI-modified
1 . A thin film transistor (TFT) array substrate, comprising:
 a substrate;   a first patterned conductive layer disposed on the substrate, wherein the first patterned conductive layer comprises a scan line, a gate electrode, and a float electrode, and the gate electrode is electrically connected to the scan line;   a first insulation layer disposed on the first patterned conductive layer;   a semiconductor layer disposed on the first insulation layer, wherein the semiconductor layer comprises a channel area;   a second patterned conductive layer disposed on the first insulation layer, the second patterned conductive layer comprising a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode, wherein the gate electrode, the source electrode, the drain electrode, and the channel area constructing a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the float electrode;   a second insulation layer disposed on the second patterned conductive layer;   a contact hole passing through the second insulation layer and exposing a portion of the extended electrode of the drain electrode; and   a pixel electrode electrically connected to the extended electrode of the drain electrode through the contact hole.   
     
     
         2 . The TFT array substrate of  claim 1 , wherein the semiconductor layer further comprises a first semiconductor area located between the extended electrode of the drain electrode and the first insulation layer. 
     
     
         3 . The TFT array substrate of  claim 2 , wherein the first semiconductor area and the channel area are connected to each other. 
     
     
         4 . The TFT array substrate of  claim 2 , wherein the first semiconductor area and the channel area are separated. 
     
     
         5 . The TFT array substrate of  claim 1 , wherein an edge of the extended electrode of the drain electrode is substantially aligned with an edge of the float electrode. 
     
     
         6 . The TFT array substrate of  claim 1 , wherein a projection position of an edge of the extended electrode located away from the drain electrode shrinks a distance from an edge of the float electrode located away from the gate electrode, and the distance is ranged between about 0 μm and about 10 μm. 
     
     
         7 . The TFT array substrate of  claim 1 , wherein a projection position of an edge of the extended electrode located away from the drain electrode protrudes a distance from an edge of the float electrode located away from the gate electrode, and the distance is ranged between about 0 μm and about 10 μm. 
     
     
         8 . The TFT array substrate of  claim 1 , wherein a height between a surface of the substrate and a top surface of the extended electrode exposed through the contact hole is ranged between about 3700 Å and about 14000 Å. 
     
     
         9 . The TFT array substrate of  claim 2 , wherein a height between a surface of the substrate and a bottom surface of the extended electrode contacting the first semiconductor area is ranged between about 1500 Å and about 10000 Å. 
     
     
         10 . The TFT array substrate of  claim 1 , wherein the float electrode is formed in a shape of square, polygon, ellipse, or circle. 
     
     
         11 . The TFT array substrate of  claim 1 , wherein the second insulation layer is formed from an organic or inorganic material. 
     
     
         12 . The TFT array substrate of  claim 1 , further comprising a third insulation layer disposed above the second insulation layer. 
     
     
         13 . The TFT array substrate of  claim 12 , wherein the third insulation layer is formed from an organic or inorganic material. 
     
     
         14 . The TFT array substrate of  claim 12 , wherein the third insulation layer is a color filter layer. 
     
     
         15 . The TFT array substrate of  claim 1 , wherein the second insulation layer is a color filter layer. 
     
     
         16 . A TFT array substrate, comprising:
 a substrate;   a first patterned conductive layer disposed on the substrate, wherein the first patterned conductive layer comprises a scan line and a gate electrode, and the gate electrode is electrically connected to the scan line;   a first insulation layer disposed on the first patterned conductive layer;   a semiconductor layer disposed on the first insulation layer, wherein the semiconductor layer comprises a channel area and a first semiconductor area;   a second patterned conductive layer disposed on the first insulation layer, the second patterned conductive layer comprising a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode, wherein the gate electrode, the source electrode, the drain electrode, and the channel area constructing a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the first semiconductor area;   a second insulation layer disposed on the second patterned conductive layer;   a contact hole passing through the second insulation layer and exposing a portion of the extended electrode of the drain electrode; and   a pixel electrode electrically connected to the extended electrode of the drain electrode through the contact hole.   
     
     
         17 . The TFT array substrate of  claim 16 , wherein the first semiconductor area is separated from the channel area. 
     
     
         18 . The TFT array substrate of  claim 16 , wherein the first semiconductor area and the channel area are connected to each other. 
     
     
         19 . The TFT array substrate of  claim 16 , wherein a height between a surface of the substrate and a top surface of the extended electrode exposed through the contact hole is ranged between about 3200 Å and about 13500 Å. 
     
     
         20 . The TFT array substrate of  claim 16 , wherein a height between a surface of the substrate and a bottom surface of the extended electrode contacting the first semiconductor area is ranged between about 1000 Å and about 9500 Å. 
     
     
         21 . The TFT array substrate of  claim 16 , wherein the second insulation layer is formed from an organic or inorganic material. 
     
     
         22 . The TFT array substrate of  claim 16 , further comprising a third insulation layer disposed above the second insulation layer. 
     
     
         23 . The TFT array substrate of  claim 22 , wherein the third insulation layer is formed from an organic or inorganic material. 
     
     
         24 . The TFT array substrate of  claim 22 , wherein the third insulation layer is a color filter layer. 
     
     
         25 . The TFT array substrate of  claim 16 , wherein the second insulation layer is a color filter layer.

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