Process for producing an mos transistor and corresponding integrated circuit

Abstract

A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced. An upper surface of the substrate and an upper surface of the isolating region are flush with each other so as to define a planar surface on which the transistor gate region is formed.

1 . An integrated circuit, comprising:
 an MOS transistor having a gate region formed on top of a silicon on insulator (SOI) substrate deposited on top of a buried oxide layer between mutually opposed zones of an isolating region defining an active zone in which the transistor is formed,   wherein an upper surface of the isolating region is flush with an upper surface of the silicon on insulator substrate so that the gate region lies across the silicon on insulator substrate and the isolating region on a planar surface.   
   
   
       2 . The circuit according to  claim 1 , wherein the isolating region is made of a material of the same type as that of the spacers for the gate. 
   
   
       3 . The circuit according to  claim 2 , wherein the material of the isolating region and spacers for the gate is a silicon nitride. 
   
   
       4 . The circuit according to  claim 3 , wherein the silicon nitride in the isolating region is compressive silicon nitride, the MOS transistor having a strained channel. 
   
   
       5 . The circuit according to  claim 3 , wherein the silicon nitride in the isolating region is tensile silicon nitride, the MOS transistor having a strained channel. 
   
   
       6 . The circuit according to  claim 1 , wherein the gate region is defined by a gate oxide lying on the planar surface and a conductive gate material lying on the gate oxide. 
   
   
       7 . The circuit according to  claim 6 , wherein the gate oxide is made of a grown single crystal material. 
   
   
       8 . The circuit according to  claim 1 , wherein the buried oxide layer has a thickness of about 200 Angstroms. 
   
   
       9 . The circuit according to  claim 1 , wherein the buried oxide layer has a thickness less than about 200 Angstroms. 
   
   
       10 . The circuit according to  claim 1 , wherein the buried oxide layer has a thickness of about 100 Angstroms. 
   
   
       11 . An integrated circuit, comprising:
 a buried oxide layer;   a silicon on insulator substrate formed on top of the buried oxide layer, the silicon on insulator substrate having an upper surface and including a source region, a drain region and a channel region;   an isolation region formed on top of the buried oxide layer defining an active region of the silicon on insulator substrate which contains the source region, drain region and channel region, the isolation region having an upper surface which is flush with the upper surface of the silicon on insulator substrate; and   a transistor gate structure formed over the channel region on a planar surface defined by the flush upper surfaces of the silicon on insulator substrate and isolation region.   
   
   
       12 . The circuit according to  claim 11 , further comprising side wall spacers on opposite sides of the transistor gate structure, the sidewall spacers being made of a material which is a same material as a material used to form the isolation region. 
   
   
       13 . The circuit according to  claim 11 , wherein the transistor gate structure is defined by a gate oxide lying on the planar surface and a conductive gate material lying on the gate oxide. 
   
   
       14 . The circuit according to  claim 13 , wherein the gate oxide is made of a grown single crystal material. 
   
   
       15 . The circuit according to  claim 11 , wherein a material used to form the isolation region is a compressive material which causes the channel region to be a strained channel region. 
   
   
       16 . The circuit according to  claim 11 , wherein a material used to form the isolation region is a tensile material which causes the channel region to be a strained channel region. 
   
   
       17 . The circuit according to  claim 11 , wherein the buried oxide layer has a thickness of about 200 Angstroms. 
   
   
       18 . The circuit according to  claim 11 , wherein the buried oxide layer has a thickness less than about 200 Angstroms. 
   
   
       19 . The circuit according to  claim 11 , wherein the buried oxide layer has a thickness of about 100 Angstroms.