Method of manufacturing flash memory device

Abstract

A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region. In addition, damage to a tunnel oxide film, a semiconductor substrate or a floating gate while an isolation film is etched at a predetermined depth in order to control the EFH can be prevented by controlling the EFH in such a manner than conductive layer spacers are formed on sidewalls of the floating gate and the isolation film is further etched.

1 . A method of manufacturing a flash memory device, comprising:
 providing a semiconductor substrate having an isolation film, a tunnel oxide film and a first conductive layer;   etching an upper portion of the isolation film to expose sidewalls of the first conductive layer; and   forming conductive layer spacers on both sides of the isolation film, the conductive layer spacers contacting with the sidewalls of the first conductive layer.   
   
   
       2 . The method of  claim 1 , comprising forming the first conductive layer to a thickness of 700 Å to 1500 Å using an undoped polysilicon film. 
   
   
       3 . The method of  claim 1 , comprising forming the conductive layer spacers using a doped polysilicon film to a thickness which is up to half the distance between neighboring cells and which does not influence an interference phenomenon between neighboring cells. 
   
   
       4 . The method of  claim 3 , wherein the doped polysilicon film for forming the conductive layer spacers has a doping concentration of at least 1E15 ions/cm 2 . 
   
   
       5 . The method of  claim 4 , wherein the doped polysilicon film for forming the conductive layer spacers has a doping concentration of 1E15 ions/cm 2  to 2E15 ions/cm 2 . 
   
   
       6 . The method of  claim 4 , wherein the doped polysilicon film for forming the conductive layer spacers has a doping concentration of more than 2E15 ions/cm 2 . 
   
   
       7 . The method of  claim 1 , further comprising etching the isolation film. 
   
   
       8 . The method of  claim 7 , comprising etching the isolation film exposed between the conductive layer spacers.