Semiconductor device and stacked semiconductor device in which circuit board and semiconductor chip are connected by leads

Abstract

A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.

1 . A semiconductor device comprising:
 a wiring circuit board;   a semiconductor chip mounted on the wiring circuit board;   a die attach material provided between the wiring circuit board and the semiconductor chip;   a wiring layer formed on one surface of the wiring circuit board;   leads extending from the wiring layer and connected to the semiconductor chip; and   bumps provided on the wiring circuit board at outer positions relative to the region where the semiconductor chip is mounted,   wherein the wiring layer in the wiring circuit board is formed on the surface opposed to the surface on which the semiconductor chip is mounted.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the leads extend from the wiring layer in the thickness direction of the wiring circuit board. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein the semiconductor chip is mounted on the wiring circuit board with spaces left at least in the vicinities of both sides on the wiring circuit board, and
 the bumps are formed in the vicinities of the both sides on the wiring circuit board.   
   
   
       4 . The semiconductor device according to  claim 1 , wherein a through hole is formed through the wiring circuit board and the die attach material, and
 the leads are passed through the through hole and electrically connected to the semiconductor chip.   
   
   
       5 . The semiconductor device according to  claim 4 , wherein the through hole is filled with a sealing material. 
   
   
       6 . The semiconductor device according to  claim 1 , wherein another wiring layer is formed on the other surface of the wiring circuit board. 
   
   
       7 . The semiconductor device according to  claim 1 , wherein the bumps are provided on the surface of the wiring circuit board on which the semiconductor chip is mounted. 
   
   
       8 . The semiconductor device according to  claim 1 , wherein the wiring circuit board is a flexible wiring circuit board. 
   
   
       9 . The semiconductor device according to  claim 1 , wherein an insulating layer is formed on the wiring layer in the wiring circuit board. 
   
   
       10 . The semiconductor device according to  claim 1 , wherein the die attach material is a die attach film or a die attach paste. 
   
   
       11 . A stacked semiconductor device comprising a plurality of semiconductor devices according to  claim 1 , wherein the plurality of semiconductor devices are stacked with the bumps of the semiconductor devices interposed between the semiconductor devices. 
   
   
       12 . The stacked semiconductor device according to  claim 11 , wherein the bumps formed on the wiring circuit boards that are present in the semiconductor devices in the uppermost and lowermost layers have are larger than the bumps positioned in the other layers. 
   
   
       13 . A semiconductor device comprising:
 a package substrate including a base member comprising a first surface including a first region and a second region provided outside of the first region and a second surface opposed to the first surface and including third and fourth regions corresponding respectively to the first and second regions, the base member further comprising an opening penetrating therethrough between respective parts of the first and third regions, the package substrate further including a plurality of wiring patterns formed on the first surface and a plurality of leads each extended from an associated one of the wiring patterns over the opening;   a semiconductor chip including a plurality of electrodes formed thereon; the semiconductor chip being mounted over the third region of the second surface of the base member of the package substrate such that the electrodes of the semiconductor chip are exposed via through opening of the base member, each of the leads of the package substrate being bent in the opening to be connected to an associated one of the electrodes of the semiconductor chip; and   a plurality of bump electrodes formed over one of the second region of the first surface and the fourth region of the second surface of the base member of the package substrate and electrically connected to the wiring patterns.   
   
   
       14 . The device as claimed in  claim 13 , wherein the package substrate further includes a conductive pattern formed on the second surface of the base member, the conductive pattern being sandwiched between the wiring patterns and the semiconductor chip. 
   
   
       15 . A semiconductor device comprising:
 a plurality of chip assemblies, each of the chip assemblies comprising:
 a package substrate including a base member comprising a first surface including a first region and a second region provided outside of the first region and a second surface opposed to the first surface and including third and fourth regions corresponding respectively to the first and second regions, the base member further comprising an opening penetrating therethrough between respective parts of the first and third regions, the package substrate further including a plurality of wiring patterns formed on the first surface and a plurality of leads each extended from an associated one of the wiring patterns over the opening; 
 a semiconductor chip including a plurality of electrodes formed thereon; the semiconductor chip being mounted over the third region of the second surface of the base member of the package substrate such that the electrodes of the semiconductor chip are exposed through the opening of the base member, each of the leads of the package substrate being bent in the opening to be connected to an associated one of the electrodes of the semiconductor chip; and 
 a plurality of bump electrodes formed over one of the second region of the first surface and the fourth region of the second surface of the base member of the package substrate and electrically connected to the wiring patterns; 
   the chip assemblies being stacked such that the bump electrodes of an upper one of the chip assemblies are electrically connected to the bump electrodes of a lower one of the chip assemblies.   
   
   
       16 . The device as claimed in  claim 15 , wherein the package substrate of each of the chip assemblies further includes a conductive pattern formed on the second surface of the base member, the conductive pattern being sandwiched between the wiring patterns and the semiconductor chip.