Semiconductor device and method of fabricating the same

Abstract

Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

1 . A semiconductor device comprising:
 a device isolation layer located on a semiconductor substrate to define an active region;   a gate pattern crossing over the active region and the device isolation layer;   a sidewall spacer pattern covering a sidewall of the gate pattern on the active pattern; and   a gate silicide layer covering at least a part of both sidewalls of the gate pattern on the device isolation layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the sidewall spacer pattern exposes all of both sidewalls of the gate pattern on the device isolation layer, and the gate silicide layer covers both of the exposed sidewalls of the gate pattern. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the sidewall spacer pattern covers a lower portion of both sidewalls of the gate pattern on the device isolation layer, and a width of the sidewall spacer pattern located on the device isolation layer is smaller than half of that of the sidewall spacer pattern located on the active region. 
   
   
       4 . The semiconductor device of  claim 1 , further comprising:
 a conductive line located on the device isolation layer adjacent to the active region, the conductive line being adjacent to the gate pattern;   a conductive line silicide layer covering at least both sidewalls of the conductive line;   an active silicide layer formed on the active region and contacting with a sidewall of the device isolation layer; and   a shared contact contacting with both the active silicide layer and the conductive line silicide layer.   
   
   
       5 . The semiconductor device of  claim 1 , wherein the gate pattern and the conductive line comprise a polysilicon layer doped with impurities or undoped with impurities. 
   
   
       6 - 11 . (canceled)