Semiconductor memory device capable of driving non-selected word lines to first and second potentials

Abstract

A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

1 - 84 . (canceled) 
     
     
         85 . A semiconductor device comprising a plurality of power source circuits each having an oscillation circuit and a capacitor, for generating a different potential by driving said capacitor by the oscillation signal outputted from said oscillation circuit:
 wherein at least a part of a plurality of said power source circuits shares in common said oscillation circuit, and drives different one of said capacitors by the oscillation signal outputted from said common oscillation circuit.   
     
     
         86 . A semiconductor device according to  claim 85 , wherein said power source circuit is equipped with an operation control circuit at an input portion to said capacitor drive circuit of the oscillation signal outputted from said common oscillation circuit. 
     
     
         87 . A semiconductor device according to  claim 85 , wherein said power source circuits sharing in common said oscillation circuit generate different potentials. 
     
     
         88 . A semiconductor device according to  claim 85 , wherein said common oscillation circuit outputs a plurality of oscillation signals having different phases, and said capacitor is driven by one of a plurality of said oscillation signals having different phases. 
     
     
         89 . A semiconductor device according to  claim 88 , wherein said power source circuits having said capacitor driven by a plurality of said oscillation signals having different phases generate the same potential, and the outputs of said power source circuits are connected in common. 
     
     
         90 . A semiconductor device according to  claim 89 , wherein said power circuit includes:
 an operation control circuit provided at an input portion of said oscillation signal outputted from said common oscillation circuit to said capacitor drive circuit, and switching the operating state of said power source circuit between an operating state and a non-operating state; and   a potential detecting circuit for detecting the potential generated by said power source circuit;   wherein said operation control circuit is controlled on the basis of the detection result of said potential detecting circuit.   
     
     
         91 - 92 . (canceled) 
     
     
         93 . A semiconductor device according to  claim 85 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         94 . A semiconductor device according to  claim 86 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         95 . A semiconductor device according to  claim 87 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         96 . A semiconductor device according to  claim 88 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         97 - 98 . (canceled)