Method and apparatus for reducing optical emissions in an integrated circuit

Abstract

An integrated circuit is provided with first circuitry having first and second transistors which emit light during a change in state between states of low and high resistance and second circuitry having third transistors which emit light during a change in state. The third transistors are disposed near at least one of the first and second transistors so that light emissions from the third transistors hinder optical detection of a pattern of light emitted by the first and second transistors.

1 . An integrated circuit comprising first circuitry having first and second transistors which emit light during a change in state between states of low and high resistance and second circuitry having third transistors which emit light during a change in state,
 wherein the third transistors are disposed near at least one of the first and second transistors so that light emissions from the third transistors hinder optical detection of a pattern of light emitted by the first and second transistors.   
     
     
         2 . An integrated circuit according to  claim 1 , wherein the first circuitry is configured such that timing of the change of state of the first transistor relative to the second transistor is controlled so as to prevent the first and second transistors having simultaneous intermediate resistances between the low and high resistances. 
     
     
         3 . An integrated circuit according to  claim 2 , wherein first and second clock signals are supplied to the respective first and second transistors, the timing of the change of state of each transistor being dependent on the supplied clock signal. 
     
     
         4 . An integrated circuit according to  claim 3 , wherein the second clock signal is configured to rise and fall, or fall and rise, within between adjacent rises and falls of the first clock signal. 
     
     
         5 . An integrated circuit according to  claim 1 , wherein the first circuitry is an inverter. 
     
     
         6 . An integrated circuit according to  claim 5 , wherein the first transistor is a nMOS transistor and the second transistor is a pMOS transistor.