Planar laminate substrate and method for fabricating organic laminate substrate pcbs, semiconductors, semiconductor wafers and semiconductor devices having miniaturized electrical pathways

Abstract

The present invention is a method of manufacturing miniaturized organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices that have a 50% reduction in physical dimensions with respect to prior art existing organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices. The base planar substrate has a vapor deposited 0.02 mil thick copper cladding thereon its first planar surface that has been affixed atop a hydrophillic layer, and an adhesive layer on its second planar surface. The copper cladding has sufficient peel strength and a low enough etch factor so as to allow 10 micron (or smaller) electrical trace pathways to be formed thereon when the steps of a specifically designed manufacturing methodology are followed.

1 . A planar laminate substrate for the fabrication of organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices having miniaturized electrical pathways comprised of;
 a substrate film base having a top and bottom planar face, and made of a non-fiberglass reinforced dielectric polymer resin;   a hydrophillic layer formed onto said top planar face;   a copper base layer formed thereon said hydrophillic layer; and   an adhesive layer affixed onto said bottom planar face and wherein said adhesive layer is made of said dielectric polymer in a non fully cured state.   
   
   
       2 . The planar laminate substrate of  claim 1  wherein said substrate film base has a thickness of 0.00098 inch (25μ) or less, and said copper base layer has a thickness of 0.00002 inch (5μ) or less. 
   
   
       3 . The planar laminate substrate of  claim 2  wherein said planar laminate substrate has a thickness of 0.00196 inch (50μ) or less.