Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip

Abstract

A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

1 . A method of cost sensitive die and package design comprising the steps of:
 developing a power supply intelligence strategy;   monitoring a plurality of sensed parameters; and   operating according to the strategy in response to a change in the sensed parameters.   
   
   
       2 . The method of  claim 1  wherein:
 the sensed parameters comprise process corner or temperature.   
   
   
       3 . The method of  claim 1  wherein:
 the sensed parameters comprise load dynamics, load bandwidth, load operation sequence, load power saving mode changes, load power down or power up sequences, or load self protection.   
   
   
       4 . A process corner sensor comprising:
 a power supply input;   a programmable divider receiving input from a crystal clock and a divider control and producing a reference base;   a first counter connected to the divider, receiving the reference base and producing a reference;   a transistor speed detector powered by the said power supply and producing a transistor corner time signal;   a second counter connected to the detector, receiving the transistor corner time signal and producing an transistor speed indicator; and   a process corner detection logic block connected to the first counter and the second counter, receiving the reference and indicator and producing a corner out.   
   
   
       5 . The process corner sensor as described in  claim 4  further comprising:
 a resistor capacitor speed detector powered by the said power supply and producing resistor capacitor corner time signal; and   a third counter connected to the detector, receiving the signal and producing a resistor capacitor speed indicator out;   wherein, the process corner detection logic block receives the resistor capacitor speed indicator along with the reference and transistor speed indicator and produces a transistor corner out and a resistor capacitor corner out.