Segmented-memory flash backed dram module

Abstract

A memory device for use with a primary power source, includes volatile memory including a plurality of memory segments defined by at least one starting addresses and a corresponding at least one ending address; an interface for connecting to a backup power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory based on the at least one starting address and the at least one ending address. In some aspects, there is only one starting address and one ending address and only data that is stored in the volatile memory at addresses between the one starting address and one ending address is moved to the non-volatile memory.

1 . A memory device for use with a primary power source, said memory device comprising:
 volatile memory including a plurality of memory segments defined by at least one starting addresses and a corresponding at least one ending address;   an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source;   a non-volatile memory; and   a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory based on the at least one starting address and the at least one ending address.   
     
     
         2 . The memory device of  claim 1 , wherein there is only one at least one starting address and only one at least one ending address and wherein the moving of data from the volatile memory to the non-volatile memory comprises moving only data that is stored in the volatile memory at addresses between the one starting address and one ending address. 
     
     
         3 . The memory device of  claim 2 , wherein data stored in the volatile memory at addresses between the one starting address and one ending address are at least one of key and directory data. 
     
     
         4 . The memory device of  claim 2 , wherein data stored in the volatile memory at addresses not between the one starting address and one ending address are executable data. 
     
     
         5 . The memory device of  claim 2 , wherein the controller is further programmed to detect a restoration of power of the primary power source and in response:
 wipe a segment of the volatile memory not between the one starting address and one ending address; and   move data from the non-volatile memory to a segment of the volatile memory between the one starting address and one ending address.   
     
     
         6 . The memory device of  claim 5 , wherein the wiping comprises setting to zero. 
     
     
         7 . The memory device of  claim 5 , wherein the wiping is performed before the moving of data from the non-volatile memory to the volatile memory. 
     
     
         8 . The memory device of  claim 1 , further comprising:
 an address memory for storing the at least one starting addresses and the at least one ending address; and   a configuration data bus for accessing the at least one starting addresses and the at least one ending address.   
     
     
         9 . The memory device of  claim 8 , wherein the address memory comprises registers, the configuration data bus comprises an I2C bus, and the accessing comprises reading and writing. 
     
     
         10 . The memory device of  claim 1 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs). 
     
     
         11 . The memory device of  claim 1 , wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA). 
     
     
         12 . The memory device of  claim 1 , wherein power from the backup power source is primarily from a capacitor. 
     
     
         13 . The memory device of  claim 1 , wherein power from the backup power source is primarily from a super capacitor. 
     
     
         14 . A method comprising:
 detecting a power failure of a primary power source of a volatile memory comprising a plurality of memory segments defined by at least one starting addresses and a corresponding at least one ending address; and   in response to detecting the power failure and while powering the volatile memory with a backup power source: moving data stored in the volatile memory to a non-volatile memory based on the at least one starting address and at least one ending address.   
     
     
         15 . The method  claim 14 , wherein there is only one at least one starting address and only one at least one ending address and wherein the moving of data from the volatile memory to the non-volatile memory comprises moving only data that is stored in the volatile memory at addresses between the one starting address and one ending address. 
     
     
         16 . The method  claim 15 , further comprising:
 detecting a restoration of power of the primary power source and in response:
 wiping a segment of the volatile memory not between the one starting address and one ending address; and 
 moving data from the non-volatile memory to a segment of the volatile memory between the one starting address and one ending address. 
   
     
     
         17 . The method claim of  16 , wherein the wiping comprises setting to zero. 
     
     
         18 . The method claim of  15 , wherein data stored in the volatile memory at addresses between the one starting address and one ending address are at least one of key and directory data and wherein data stored in the volatile memory at addresses not between the one starting address and one ending address are executable data. 
     
     
         19 . The method of  claim 14 , further comprising setting the at least one starting address and at least one ending address based on input from a host system. 
     
     
         20 . The method of  claim 19 , wherein the input from the host system is received from an Inter-Integrated Circuit bus.