Method of reading memory cell

Abstract

A method for reading a memory cell ( 20 ) of a semiconductor memory ( 10 ) includes initiating a precharge or predischarge operation on a bit line ( 24 ) prior to arrival of a triggering edge of a clock signal ( 32 ) that initiates a read operation. A word line ( 22 ) is activated responsive to the triggering edge of the clock signal ( 32 ), and data is read from the memory cell ( 20 ).

1 . A method for reading a memory cell of a semiconductor memory, comprising:
 initiating a precharge or predischarge operation on a bit line prior to arrival of a triggering edge of a clock signal that initiates a read operation;   activating a word line responsive to the triggering edge of the clock signal; and   reading data from the memory cell.   
     
     
         2 . The method for reading a memory cell of a semiconductor memory of  claim 1 , further comprising terminating the precharge or predischarge operation before activating the word line. 
     
     
         3 . The method for reading a memory cell of a semiconductor memory of  claim 1 , wherein the precharge or predischarge operation is initiated a worst case setup time before the arrival of the triggering edge of the clock signal. 
     
     
         4 . The method for reading a memory cell of a semiconductor memory of  claim 3 , wherein the precharge or predischarge operation is initiated between about 400 picoseconds (ps) and about 800 ps before the arrival of the triggering edge of the clock signal. 
     
     
         5 . The method for reading a memory cell of a semiconductor memory of  claim 1 , wherein the precharge or predischarge operation is performed during a setup time of the semiconductor memory. 
     
     
         6 . The method for reading a memory cell of a semiconductor memory of  claim 1 , wherein the precharge or predischarge operation is initiated by asserting a chip enable signal. 
     
     
         7 . The method for reading a memory cell of a semiconductor memory of  claim 1 , wherein the precharge or predischarge operation is initiated by asserting an asynchronous signal or pin. 
     
     
         8 . The method for reading a memory cell of a semiconductor memory of  claim 1 , wherein the semiconductor memory is a zero current leakage type read-only memory (ROM). 
     
     
         9 . A method for reading a memory cell of a zero current leakage type read-only memory (ROM), comprising:
 initiating a precharge or predischarge operation on a bit line prior to arrival of a triggering edge of a clock signal that initiates a read operation;   activating a word line responsive to the triggering edge of the clock signal; and   reading data from the memory cell.   
     
     
         10 . The method for reading a memory cell of a zero current leakage type ROM of  claim 9 , further comprising terminating the precharge or predischarge operation before activating the word line. 
     
     
         11 . The method for reading a memory cell of a zero current leakage type ROM of  claim 9 , wherein the precharge or predischarge operation is initiated a worst case setup time before the arrival of the triggering edge of the clock signal. 
     
     
         12 . The method for reading a memory cell of a zero current leakage type ROM of  claim 11 , wherein the precharge or predischarge operation is initiated between about 400 ps and about 800 ps before the arrival of the triggering edge of the clock signal. 
     
     
         13 . The method for reading a memory cell of a zero current leakage type ROM of  claim 9 , wherein the precharge or predischarge operation is performed during a setup time of the ROM. 
     
     
         14 . The method for reading a memory cell of a zero current leakage type ROM of  claim 9 , wherein the precharge or predischarge operation is initiated by asserting a chip enable signal. 
     
     
         15 . The method for reading a memory cell of a zero current leakage type ROM of  claim 9 , wherein the precharge or predischarge operation is initiated by asserting an asynchronous signal or pin. 
     
     
         16 . The method for reading a memory cell of a zero current leakage type ROM of  claim 9 , wherein a gate count along a path from a clock input to the word line is less than or equal to about six (6) gates. 
     
     
         17 . A method for reading a memory cell of a zero current leakage type read-only memory (ROM), comprising: initiating a precharge or predischarge operation on a bit line prior to arrival of a triggering edge of a clock signal that initiates a read operation;
 terminating the precharge or predischarge operation prior to word line activation;   activating a word line responsive to the triggering edge of the clock signal; and   reading data from the memory cell.   
     
     
         18 . The method for reading a memory cell of a zero current leakage type ROM of  claim 17 , wherein the precharge or predischarge operation is initiated a worst case setup time before the arrival of the triggering edge of the clock signal. 
     
     
         19 . The method for reading a memory cell of a zero current leakage type ROM of  claim 17 , wherein the precharge or predischarge operation is performed during a setup time of the ROM. 
     
     
         20 . The method for reading a memory cell of a zero current leakage type ROM of  claim 17 , wherein a gate count along a path from a clock input to the word line is less than or equal to about six (6) gates.