Multi-level power supply system for a complementary metal oxide semiconductor

Abstract

There is provided a method that includes comparing a voltage level (Vs 1 ) of a lower voltage supply bus to a voltage level (Vs 2 ) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs 2 <Vs 1 . The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. There is also provided a circuit that employs the method.

1 . A method, comprising:
 comparing a voltage level (Vs 1 ) of a lower voltage supply bus to a voltage level (Vs 2 ) of a higher voltage supply bus; and   routing current from said lower voltage supply bus to said higher voltage supply bus if Vs 2 <Vs 1 ,   wherein said lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit.   
   
   
       2 . The method of  claim 1 , wherein said comparing is performed by a device that is powered by said lower voltage supply bus. 
   
   
       3 . The method of  claim 1 , wherein said routing of said current continues until Vs 2 ≧Vs 1 . 
   
   
       4 . The method of  claim 1 ,
 wherein said lower voltage supply bus is a first voltage supply bus,   wherein said higher voltage supply bus is a second voltage supply bus, and   wherein said method further comprises:
 comparing Vs 2  to a voltage level (Vs 3 ) of a third voltage supply bus; and 
 routing current from said second voltage supply bus to said third voltage supply bus if Vs 3 <Vs 2 . 
   
   
   
       5 . The method of  claim 4 ,
 wherein said third voltage supply bus also provides power to said (CMOS) circuit, and   wherein said CMOS circuit operates with Vs 3 >Vs 2 >Vs 1 .   
   
   
       6 . The method of  claim 1 , wherein said CMOS circuit includes a plurality of p-type metal oxide semiconductor devices in a common well. 
   
   
       7 . The method of  claim 6 , wherein said common well is electrically connected to said higher voltage supply bus. 
   
   
       8 . The method of  claim 1 , wherein said comparing is performed by a device having inputs for sensing Vs 1  and Vs 2 , and that employs hysteresis to said inputs. 
   
   
       9 . A circuit, comprising:
 a comparator that compares a voltage level (Vs 1 ) of a lower voltage supply bus to a voltage level (Vs 2 ) of a higher voltage supply bus; and   a switch that routes current from said lower voltage supply bus to said higher voltage supply bus if Vs 2 <Vs 1 ,   wherein said lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit.   
   
   
       10 . The circuit of  claim 9 , wherein said comparator is powered by said lower voltage supply bus. 
   
   
       11 . The circuit of  claim 9 , wherein said switch continues to route said current until Vs 2 ≧Vs 1 . 
   
   
       12 . The circuit of  claim 9 ,
 wherein said comparator is a first comparator,   wherein said switch is a first switch,   wherein said lower voltage supply bus is a first voltage supply bus,   wherein said higher voltage supply bus is a second voltage supply bus, and   wherein said circuit further comprises:
 a second comparator that compares Vs 2  to a voltage level (Vs 3 ) of a third voltage supply bus; and 
 a second switch that routes current from said second voltage supply bus to said third voltage supply bus if Vs 3 <Vs 2 . 
   
   
   
       13 . The circuit of  claim 12 ,
 wherein said third voltage supply bus also provides power to said (CMOS) circuit, and   wherein said CMOS circuit operates with Vs 3 >Vs 2 >Vs 1 .   
   
   
       14 . The circuit of  claim 9 , wherein said CMOS circuit includes a plurality of p-type metal oxide semiconductor devices in a common well. 
   
   
       15 . The circuit of  claim 14 , wherein said common well is electrically connected to said higher voltage supply bus. 
   
   
       16 . The circuit of  claim 9 , wherein said comparator includes inputs for sensing Vs 1  and Vs 2 , and employs hysteresis to said inputs.