Method for tuning the threshold voltage of a metal gate and high-k device

Abstract

A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.

1 . A method of forming a deep trench capacitor, comprising:
 providing a first wafer, the first wafer having a front side and a back side and including a substrate;   forming devices on the front side of the first wafer;   forming a through-silicon-via on the substrate;   forming a deep trench on the back side of the first wafer; and   forming a deep trench capacitor in the deep trench, wherein the through-silicon-via connects the deep trench capacitor to the devices.   
   
   
       2 . A method according to  claim 1 , wherein the first wafer is bonded to a second handle wafer. 
   
   
       3 . A method according to  claim 1 , wherein the substrate is silicon, silicon-on-insulator or gallium arsenide. 
   
   
       4 . A method of forming a deep trench capacitor comprising:
 providing a first wafer, the first wafer having a front side and a back side and including a substrate;   forming devices on the front side of the first wafer;   forming a through-silicon-via on the substrate;   thinning silicon from the back side of the first wafer to expose the through-silicon-via;   depositing a pad layer on the substrate;   forming a deep trench on the back side of the first wafer;   forming a buried plate in the substrate, wherein the buried plate contacts the through-silicon-via;   performing an anneal;   depositing a node dielectric layer in the deep trench;   filling the deep trench with a conductive material; and   depositing a conductive layer over the pad layer and the conductive material.   
   
   
       5 . A method according to  claim 4 , wherein the first wafer is bonded to a second handle wafer. 
   
   
       6 . A method according to  claim 4 , wherein the pad layer is deposited by chemical vapor deposition (CVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). 
   
   
       7 . A method according to  claim 6 , wherein the pad layer is selected from the group consisting of: silicon nitride, silicon dioxide and polysilicon. 
   
   
       8 . A method according to  claim 4 , wherein the deep trench is formed by using the pad layer as a mask and using a reactive ion etch (RIE) to form the trench. 
   
   
       9 . A method according to  claim 4 , wherein the buried plate is formed by plasma doping, thermal diffusion or ion implantation. 
   
   
       10 . A method according to  claim 4 , wherein the node dielectric layer is deposited by thermal oxidation or chemical vapor deposition (CVD). 
   
   
       11 . A method according to  claim 10 , wherein the node dielectric layer is selected from the group consisting of: silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide and hafnium silicate. 
   
   
       12 . A method according to  claim 4  wherein the conductive material is selected from the group consisting of: tungsten (W), copper (Cu) and polysilicon (poly-Si). 
   
   
       13 . A method according to  claim 4  wherein the conductive layer is selected from the group consisting of: tungsten (W), copper (Cu) and polysilicon (poly-Si). 
   
   
       14 . A method of forming a deep trench capacitor, comprising:
 providing a first wafer and a second wafer;   bonding the first wafer to the second wafer;   fabricating a through-silicon-via in the first and second wafers;   metalizing the through-silicon-via;   forming a recess above the through-silicon-via;   filling the recess with a non-conductive material;   forming a deep trench in a substrate on the second wafer;   forming a buried plate in the substrate, wherein the through-silicon-via contacts the buried plate and wiring on the first wafer; and   filling the deep trench with a conductive material.   
   
   
       15 . A method according to  claim 14 , wherein the first wafer is bonded to the second wafer by an adhesive bond, an oxide to oxide bond or a metal to metal bond. 
   
   
       16 . A method according to  claim 14 , wherein the first wafer is bonded to the second wafer by a metal to metal bond and a bonding metal on the first and second wafers is patterned to create a keep out area. 
   
   
       17 . A deep trench capacitor, comprising:
 a wafer;   devices formed on a front side of the wafer;   a through-silicon-via formed on a substrate of the wafer;   a deep trench formed on a back side of the wafer; and   a deep trench capacitor formed in the deep trench, wherein the through-silicon-via connects the deep trench capacitor to the devices.   
   
   
       18 . A deep trench capacitor, comprising:
 a substrate;   a through-silicon-via formed on the substrate;   a pad layer deposited on the substrate;   a deep trench formed in the substrate;   a buried plate formed in the substrate, wherein the buried plate is electrically connected to the through-silicon-via;   a node dielectric layer deposited in the deep trench;   a conductive material filling the deep trench; and   a conductive layer deposited over the pad layer and the conductive material.   
   
   
       19 . A deep trench capacitor according to  claim 18 , wherein the substrate is bonded to a handle wafer. 
   
   
       20 . A deep trench capacitor, comprising:
 a first wafer bonded to a second wafer;   a through-silicon-via fabricated in the first and second wafers, wherein the through-silicon-via is metalized;   a deep trench formed in a substrate of the second wafer;   a buried plate formed in the substrate, wherein the through-silicon-via contacts the buried plate and wiring on the first wafer;   a recess above the through-silicon-via, wherein the recess is filled with a non-conductive material; and   a conductive material filling the deep trench.   
   
   
       21 . A deep trench capacitor according to  claim 20 , further comprising a keep out area, wherein the through-silicon-via passes through the keep out area.