Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

1 - 15 . (canceled) 
   
   
       16 . A method comprising:
 forming first and second gate structures over a semiconductor substrate to make a space between the first and second gate structures, the space being defined by side surfaces of the first and second gate electrode structures facing with each other, each of the first and second gate electrode structures having an upper surface;   forming first and second sidewalls respectively on the side surfaces of the first and second gate structures, each of the first and second side walls including a first part on a side of the semiconductor substrate and a second part on a side of the upper surface thereof;   forming a silicon layer in the space over the semiconductor substrate and in contact respectively with the first parts of the first and second side walls;   forming third and fourth sidewalls in contact respectively with the second parts of the first and second side walls and with the silicon layer with leaving a portion of the silicon layer between the third and fourth sidewalls; and   forming a conductive member over the silicon layer, the conductive member being in touch with the third and fourth sidewalls.   
   
   
       17 . The method as claimed in  claim 16 , wherein the conductive member includes a first portion in touch with the third and fourth sidewalls and a second portion covering a surface of the first portion. 
   
   
       18 . The method as claimed in  claim 17 , wherein the first and second portions are different in material from each other. 
   
   
       19 . The method as claimed in  claim 16 , wherein the first and second sidewalls are the same in material as each other, the third and fourth sidewalls being the same in material as each other, and the first and second sidewalls being different in material from the third and fourth sidewalls. 
   
   
       20 . The method as claimed in  claim 16 , wherein each of the first and second sidewalls includes a silicon oxide film and each of the third and fourth sidewalls includes a silicon nitride film. 
   
   
       21 . The method as claimed in  claim 17 , wherein the first portion includes lamination of a titanium film and a titunium nitride film. 
   
   
       22 . The method as claimed in  claim 17 , wherein the second portion includes tungsten. 
   
   
       23 . The method as claimed in  claim 16 , wherein the silicon layer is formed by selective epitaxial growth. 
   
   
       24 . The method as claimed in  claim 16 , wherein each of the first and second gate structures includes a polysilicon film and a tungsten silicide film. 
   
   
       25 . The method as claimed in  claim 16 , wherein the silicon layer includes phosphorus. 
   
   
       26 . A method comprising:
 providing a semiconductor body including a first portion, a second portion and a third portion between the first and second portions, the third portion including first and second edge parts respectively on sides of the first and second portions an a central part between the first and second edge parts;   forming first and second gate electrode structures respectively over the first and second portions of the semiconductor body, each of the first and second gate electrode structures including an upper surface and a side surface;   forming first and second sidewalls respectively over the side surfaces of the first and second gate electrode structures with respectively covering the first and second edge parts of the third portion;   forming a silicon layer on the central part of the third portion up to a level that is lower in height than the upper surface of each of the first and second gate electrode structures, the silicon layer including first and second parts respectively on sides of the first and second sidewalls and a third part between the first and second parts;   forming third and fourth sidewalls respectively over the first and second sidewalls with respectively covering the first and second parts of the silicon layer; and   forming a conductive layer on the third part of the silicon layer and in contact the third and fourth sidewalls.   
   
   
       27 . The method as claimed in  claim 26 , wherein further comprising an impurity diffusion region in the third portion of the semiconductor body before the forming the first and second sidewalls. 
   
   
       28 . The method as claimed in  claim 26 , wherein each of the forming the first and second sidewalls and the forming the third and fourth sidewalls comprises forming an insulating layer over an entire surface and then performing an anisotropic etching on the insulating layer. 
   
   
       29 . The method as claimed in  claim 26 , wherein the forming the conductive layer comprises forming a metal silicide film on the third part of the silicon layer and forming a metal layer on the metal silicide layer. 
   
   
       30 . A semiconductor device comprising:
 first and second gate structures over a semiconductor substrate to make a space between the first and second gate structures, the space being defined by side surfaces of the first and second gate electrode structures facing with each other, each of the first and second gate electrode structures having an upper surface;   first and second sidewalls respectively on the side surfaces of the first and second gate structures, each of the first and second side walls including a first part on side of the semiconductor substrate and a second part onside of the upper surface thereof;   a silicon layer in the space over the semiconductor substrate and in contact respectively with the first parts of the first and second side walls;   third and fourth sidewalls in contact respectively with the second parts of the first and second side walls and with the silicon layer with leaving a portion of the silicon layer between the third and fourth sidewalls; and   a conductive member over the silicon layer, the conductive member being in touch with the third and fourth sidewalls.   
   
   
       31 . The semiconductor device as claimed in  claim 30 , wherein the conductive member includes a first portion in touch with the third and fourth sidewalls and a second portion covering a surface of the first portion. 
   
   
       32 . The semiconductor device as claimed in  claim 31 , wherein the first and second portions are different in material from each other. 
   
   
       33 . The semiconductor device as claimed in  claim 30 , wherein the first and second sidewalls are the same in material as each other, the third and fourth sidewalls being the same in material as each other, and the first and second sidewalls being different in material from the third and fourth sidewalls. 
   
   
       34 . The semiconductor device as claimed in  claim 30 , wherein each of the first and second sidewalls includes a silicon oxide film and each of the third and fourth sidewalls includes a silicon nitride film. 
   
   
       35 . The semiconductor device as claimed in  claim 31 , wherein the first portion includes lamination of a titanium film and a titunium nitride film.