Super gto-based power blocks

Abstract

A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces. Upper metal stripes extend along the upper surface of the insulator, and lower metal stripes extend along the lower surface of the insulator. The upper and lower metal stripes are connected together by vias that extend through the insulator. One set of the lower metal stripes contacts the first conductive contacts, but not the second conductive contacts. Another set of the lower metal stripes contacts the second conductive contacts, but not the first conductive contacts.

1 . A gate turn-off thyristor device comprising:
 a lower portion having at least one lower base region of a first conductivity type, at least one lower emitter region of a second conductivity type disposed at or from a lower surface of said at least one lower base region, and at least one lower junction formed between the at least one lower base region and the at least one lower emitter region;   an upper portion having at least one upper base region of the second conductivity type, at least one upper emitter region of the first conductivity type disposed at or from an upper surface of the at least one upper base region, and at least one upper junction formed between the at least one upper base region and the at least one upper emitter region, wherein the at least one upper base region and at least one upper emitter region are arranged to form at least one upper surface of the upper portion with first conductive contacts to the at least one upper base region alternating with second conductive contacts to the at least one upper emitter region;   an upper-lower junction formed between said at least one lower base region and said at least one upper base region; the lower junction, upper junction and upper-lower junctions forming a junction series through which forward current can flow in a latched-on condition; and,   a lid comprising a layer of insulator with upper and lower surfaces, at least one upper metal stripe extending along the upper surface of the insulator, at least one lower metal stripe extending along the lower surface of the insulator, wherein a first one of the at least one lower metal stripe contacts at least two of the first conductive contacts but not the second conductive contacts, and a second one of the at least one lower metal stripe contacts at least two of the second conductive contacts but not the first conductive contacts, said lid further comprising conductive vias connecting the at least one upper metal stripe with the at least one lower metal stripe, wherein the upper junction, upper surface of the upper portion, first and second conductive contacts and vias enhance current flow uniformity and minimize inductance.   
   
   
       2 . The device of  claim 1 , wherein the at least one upper emitter region comprises at least one finger having a width of less than 100 microns. 
   
   
       3 . The device of  claim 1 , wherein the upper surface of the at least one upper base region comprises a finger having a width of less than 100 microns. 
   
   
       4 . The device of  claim 1 , further comprising an intermediate layer having at least one first region of a first metal alternating with at least one second region of a second metal and non-conductivity regions therebetween, the first region of said intermediate layer connected to the first conductive contacts and the second region of said intermediate layer connected to the second conductive contacts. 
   
   
       5 . The device of  claim 4 , further comprising a dielectric layer with openings formed over said intermediate layer and first and second metal stripes formed over said dielectric layer and contacting a respective one of the first and second regions of said intermediate layer through the openings in said dielectric layer. 
   
   
       6 . The device of  claim 1 , wherein the said first and second ones of the lower metal stripes cross with said upper emitter regions. 
   
   
       7 . The device of  claim 1 , wherein the upper and lower metal stripes are elongated, and the upper metal stripes cross with the lower metal stripes. 
   
   
       8 . The device of  claim 1 , wherein the first and second conductive contacts have a combined total width of less than 0.5 cm. 
   
   
       9 . The device of  claim 1 , wherein each lower metal stripe contacts at least two of the first and second conductive contacts. 
   
   
       10 . The device of  claim 1 , wherein at least one upper metal stripe connects to one or more electrodes on a control device mounted on said lid. 
   
   
       11 . The device of  claim 1 , the lower portion comprising a substrate wafer, wherein the upper base region and upper emitter regions are diffused from an upper surface of the wafer to form planar junctions. 
   
   
       12 . The device of  claim 1 , wherein said upper portion comprises a dense arrangement of upper emitter regions. 
   
   
       13 . The device of  claim 1 , wherein the first and second conductive contacts alternate in a regular repeating form. 
   
   
       14 . The device of  claim 1 , wherein said gate turn-off thyristor turns off a current density of at least 500 A/cm 2 . 
   
   
       15 . The device of  claim 1 , wherein the at least one upper emitter region has a repeating pattern along a cell of good and moderate injection regions, and/or good and moderate contact impedance regions, and/or wider and narrower emitter regions. 
   
   
       16 . The device of  claim 1 , wherein a control device is mounted on said lid, the control device controlling said gate turn-off thyristor device. 
   
   
       17 . The device of  claim 1 , further comprising a controlled thyristor connected to the at least one upper base region and providing fast turn on of said gate turn-off thyristor device. 
   
   
       18 . The device of  claim 1 , further comprising an integrated gate controlled transistor connected to the at least one upper base region. 
   
   
       19 . A gate turn-off thyristor device comprising:
 a lower portion having at least one lower base region of a first conductivity type, and at least one lower emitter region of a second conductivity type disposed at or from a lower surface of said at least one lower base region;   an upper portion having at least one upper base region of the second conductivity type, and at least one upper emitter region of the first conductivity type disposed at or from an upper surface of the at least one upper base region, wherein the at least one upper base region and at least one upper emitter region are arranged to form an upper surface with first conductive contacts to the at least one upper base region alternating with second conductive contacts to the at least one upper emitter region; and,   a lid comprising a layer of insulator with upper and lower surfaces, upper metal stripes extending along the upper surface of the insulator, lower metal stripes extending along the lower surface of the insulator, wherein a first one of the lower metal stripes contacts at least two of the first conductive contacts but not the second conductive contacts, and a second one of the lower metal stripes contacts at least two of the second conductive contacts but not the first conductive contacts, said lid further comprising conductive vias connecting the upper metal stripes with the lower metal stripes.   
   
   
       20 . The device of  claim 19 , wherein the at least one upper emitter region comprises at least one finger having a width of less than  100  microns. 
   
   
       21 . The device of  claim 19 , wherein the upper surface of the at least one upper base region comprises a finger having a width of less than  100  microns. 
   
   
       22 . The device of  claim 19 , further comprising an intermediate layer having at least one first region of a first metal alternating with at least one second region of a second metal and non-conductivity regions therebetween, the first region of said intermediate layer connected to the first conductive contacts and the second region of said intermediate layer connected to the second conductive contacts. 
   
   
       23 . The device of  claim 22 , further comprising a dielectric layer with openings formed over said intermediate layer and first and second metal stripes formed over said dielectric layer and contacting a respective one of the first and second regions of said intermediate layer through the openings in said dielectric layer. 
   
   
       24 . The device of  claim 19 , wherein the said first and second ones of the lower metal stripes cross with said upper emitter regions. 
   
   
       25 . The device of  claim 19 , wherein the upper and lower metal stripes are elongated, and the upper metal stripes cross with the lower metal stripes. 
   
   
       26 . The device of  claim 19 , wherein the first and second conductive contacts have a combined total width of less than 0.5 cm. 
   
   
       27 . The device of  claim 19 , wherein each lower metal stripe contacts at least two of the first and second conductive contacts. 
   
   
       28 . The device of  claim 19 , wherein at least one upper metal stripe connects to one or more electrodes on a control device mounted on said lid. 
   
   
       29 . The device of  claim 19 , the lower portion comprising a substrate wafer, wherein the upper base region and upper emitter regions are diffused from an upper surface of the wafer to form planar junctions. 
   
   
       30 . The device of  claim 19 , wherein said upper portion comprises a dense arrangement of upper emitter regions. 
   
   
       31 . The device of  claim 19 , wherein the first and second conductive contacts alternate in a regular repeating form. 
   
   
       32 . The device of  claim 19 , wherein said gate turn-off thyristor turns off a current density of at least 500 A/cm 2 . 
   
   
       33 . The device of  claim 19 , wherein the at least one upper emitter region has a repeating pattern along a cell of good and moderate injection regions, and/or good and moderate contact impedance regions, and/or wider and narrower emitter regions. 
   
   
       34 . The device of  claim 19 , wherein a control device is mounted on said lid, the control device controlling said gate turn-off thyristor device. 
   
   
       35 . The device of  claim 19 , further comprising a controlled thyristor connected to the at least one upper base region and providing fast turn on of said gate turn-off thyristor device. 
   
   
       36 . The device of  claim 19 , further comprising an integrated gate controlled transistor connected to the at least one upper base region.