Non-volatile memory device and ispp programming method

Abstract

A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.

1 . A method of programming a non-volatile memory device including a plurality of non-volatile memory cells using an incremental step pulse programming (ISPP) scheme, the method comprising:
 operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated; and   operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated,   wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.   
   
   
       2 . The method of  claim 1 , wherein the predetermined condition is a number of pass cells or a number of fail cells determined during the verify operation. 
   
   
       3 . The method of  claim 1 , wherein the plurality of non-volatile memory cells are multi-level cell (MLC) memory cells. 
   
   
       4 . The method of  claim 1 , wherein during the second program mode, the program pulse width is doubled for each successive ISPP cycle. 
   
   
       5 . The method of  claim 4 , wherein during the second program mode, the program voltage is constant at the maximum value. 
   
   
       6 . The method of  claim 1 , wherein during the second program mode, the program pulse is successively increased per ISPP cycle by applying an increasing number of sub pulses having a constant sub pulse width per ISPP cycle. 
   
   
       7 . The method of  claim 6 , wherein during the second program mode, the program voltage is constant at the maximum value. 
   
   
       8 . The method of  claim 1 , wherein a bit line program inhibition voltage applied to a bit line connected to a program-inhibited cell and a bit line program voltage applied to a bit line connected to a program cell are constant in the first program mode; and
 the bit line program inhibition voltage applied to the bit line connected to the program-inhibited cell is constant and the bit line program voltage applied to the bit line connected to the program cell successively decreases per ISPP cycle in the second program mode.   
   
   
       9 . A method of programming a non-volatile memory device including a plurality of non-volatile memory cells using an incremental step pulse programming (ISPP) scheme, the method comprising:
 operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased by a first step voltage per ISPP cycle, and during which a program operation and a verify operation are alternately repeated; and   operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is increased by a second step voltage, and during which a program operation and a verify operation are alternately repeated,   wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or a verification result count value satisfies a predetermined condition.   
   
   
       10 . The method of  claim 9 , wherein the second step voltage is less than the first step voltage. 
   
   
       11 . The method of  claim 9 , wherein the predetermined condition is a number of pass cells or a number of fail cells determined during the verify operation. 
   
   
       12 . The method of  claim 9 , wherein the plurality of non-volatile memory cells are multi-level cell (MLC) memory cells. 
   
   
       13 . The method of  claim 9 , wherein during the second program mode, the program pulse is successively increased per ISPP cycle by applying an increasing number of sub pulses having a constant sub pulse width per ISPP cycle. 
   
   
       14 . The method of  claim 9 , wherein a bit line program inhibition voltage applied to a bit line connected to a program-inhibited cell and a bit line program voltage applied to a bit line connected to a program cell are constant in the first program mode; and
 the bit line program inhibition voltage applied to the bit line connected to the program-inhibited cell is constant and the bit line program voltage applied to the bit line connected to the program cell successively decreases per ISPP cycle in the second program mode.   
   
   
       15 . A method of programming a non-volatile memory device including a plurality of non-volatile memory cells using an incremental step pulse programming (ISPP) scheme, the method comprising:
 operating in a first program mode during which a program operation and a verify operation are alternately repeated and during which:   (a) a program pulse width is constant,   (b) a program voltage is successively increased per ISPP cycle, and   (c) a bit line program inhibition voltage applied to a bit line connected to a program-inhibited cell and a bit line program voltage applied to a bit line connected to a program cell are constant; and   operating in a second program mode during which:   (a) the program pulse width is constant,   (b) the program voltage is constant at a maximum valve, and   (c) the bit line program inhibition voltage applied to the bit line connected to the program-inhibited cell is constant and the bit line program voltage applied to the bit line connected to the program cell successively decreases per ISPP cycle,   wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.   
   
   
       16 . A method of programming a non-volatile memory cell capable of storing multilevel data in accordance with multiple program states including a low program state and a high program state using an incremental step pulse programming (ISPP) scheme, the method comprising:
 performing low-state programming in which a series of low-state program pulses, for which a pulse width is maintained constant and a program voltage is successively increased per ISPP cycle, are applied to program the non-volatile memory cell in the low program state, wherein the low-state programming comprises performing a program operation followed by a verify operation per ISPP cycle; and   performing high-state programming in which a series of high-state program pulses, for which the pulse width is successively increased per ISPP cycle and the program voltage is maintained constant, are applied to program the non-volatile memory cell in the high program state, wherein the high-state programming comprises performing the program operation followed by the verify operation per ISPP cycle,   wherein the low-state programming and the high-state programming are performed in parallel by applying one of the low-state program pulses and one of the high-state program pulses between adjacent verify pulses.   
   
   
       17 . The method of  claim 16 , wherein during the second program mode, the program pulse is successively increased per ISPP cycle by applying an increasing number of sub pulses having a constant sub pulse width per ISPP cycle. 
   
   
       18 . The method of  claim 16 , wherein a predetermined bit line program inhibition voltage is applied to a bit line connected to a program-inhibited cell and a predetermined bit line program voltage is applied to a bit line connected to a program cell during the low-state programming; and
 the predetermined bit line program inhibition voltage is applied to the bit line connected to the program-inhibited cell and a bit line program voltage decreasing in steps at each programming cycle is applied to the bit line connected to the program cell during the high-state programming.   
   
   
       19 . The method of  claim 16 , wherein the memory cell to be programmed to the high program state is prohibited from being programmed while the low-state program pulses are applied. 
   
   
       20 . The method of  claim 16 , wherein the low-state program pulses are applied to the non-volatile memory cell when programmed to the low program state and when programmed to the high program state; and
 the high-state program pulses are applied to the non-volatile memory cell only when programmed to the high program state.