Semiconductor device with dual gates and method of manufacturing the same

Abstract

In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

1 . A semiconductor device with dual gates, comprising:
 a semiconductor substrate having a first region on which a MOS transistor of a first conductivity type will be formed and a second region on which a MOS transistor of a second conductivity type will be formed;   a first gate dielectric layer on the semiconductor substrate of the first region;   a first gate electrode on the first gate dielectric layer, the first gate electrode including a lower metallic conductive pattern, an upper metallic conductive pattern, and a first polysilicon layer pattern, which are successively deposited;   a second gate dielectric layer on the semiconductor substrate of the second region;   a second gate electrode on the second gate dielectric layer, the second gate electrode including a second polysilicon layer pattern; and   wherein the lower metallic conductive pattern determines a work function of the first gate electrode.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the lower metallic conductive pattern comprises a metal containing conductive material having a work function suitable to the MOS transistor of the first conductivity type. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the lower metallic conductive pattern comprises any material selected from the group consisting of WN, TaN, TiN, Ni, Pd, Pt, Be, Ir, Te, Re, Ru and Rh. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the upper metallic conductive pattern comprises a metal containing conductive material having an etch selectivity with respect to the lower metallic conductive pattern. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the upper metallic conductive pattern comprises any material selected from the group consisting of TaN, WN, HfN, ZrN, TaSiN, TiSiN, NiSiN, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe, Ta, Ga, Hf, In, Mn, Nb, Y and Zr. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the upper metallic conductive pattern has a thickness of less than about 100 Å. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the first and second gate dielectric layers comprise a high-k dielectric. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type. 
   
   
       9 . A semiconductor device with dual gates, comprising:
 a semiconductor substrate having a first region on which a MOS transistor of a first conductivity type will be formed and a second region on which a MOS transistor of a second conductivity type will be formed;   a gate dielectric layer on the semiconductor substrate in the first and second regions;   a first gate electrode on the gate dielectric layer of the first region, the first gate electrode including a lower metallic conductive pattern, an upper metallic conductive pattern, and a first polysilicon layer pattern, which are successively deposited;   a second gate electrode on the gate dielectric layer of the second region, the second gate electrode including a second polysilicon layer pattern;   wherein the lower metallic conductive pattern comprises WN; and   wherein the upper metallic conductive pattern comprises TaN.