Microcomputer and dividing circuit

Abstract

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

1 . (canceled) 
     
     
         2 . A microcomputer formed on a single semiconductor device comprising:
 a CPU having general purpose registers and a program counter; and   a memory coupled to said CPU,   wherein the CPU is capable of processing a data transfer instruction, a conditional branch instruction and an unconditional branch instruction,   wherein each of the data transfer instruction, the conditional branch instruction and the unconditional branch instruction is of 16 bits in length,   wherein the memory stores instructions to be processed by said CPU,   wherein the conditional branch instruction includes a first area for a first displacement,   wherein the unconditional branch instruction includes a second area for a second displacement,   wherein a length of the first area of the conditional branch instruction is smaller than that of the unconditional branch instruction,   wherein the data transfer instruction includes a third area for a third displacement and a fourth area for destination register information to designate the general purpose registers where source data is to be loaded,   wherein a first branch target address of the conditional branch instruction is obtained based on the first displacement in the first area of the conditional branch instruction and an address in the program counter,   wherein a second branch target address of the unconditional branch instruction is obtained based on the second displacement in the second area of the unconditional branch instruction and an address in the program counter, and   wherein 32 bits of the source data is obtained from a memory location indicated by an address obtained based on the third displacement in the third area of the data transfer instruction and an address in the program counter, and the source data is loaded into one of the general purpose registers which is designated by the fourth area of the data transfer instruction.   
     
     
         3 . The microcomputer according to  claim 2 , wherein the third area of the data transfer instruction is of 8 bits in length. 
     
     
         4 . The microcomputer according to  claim 2 , wherein the program counter is of 32 bits in length. 
     
     
         5 . The microcomputer according to  claim 2 , wherein the general purpose registers are of 32 bits in length. 
     
     
         6 . The microcomputer according to  claim 2 , wherein the first area of the conditional branch instruction is of 8 bits in length. 
     
     
         7 . The microcomputer according to  claim 2 , wherein the second area of the unconditional branch instruction is of 12 bits in length. 
     
     
         8 . The microcomputer according to  claim 2 , wherein the memory is a cache memory. 
     
     
         9 . The microcomputer according to  claim 2 , wherein the first branch target address is obtained by adding the displacement in the first area with an address in the program counter. 
     
     
         10 . The microcomputer according to  claim 2 ,
 wherein the data transfer instruction further includes a fifth area to indicate an operation code defining a data transfer operation, and   wherein the third displacement is shifted by 2 bits and the shifted displacement is added to the address in the program counter.   
     
     
         11 . A central processing unit of RISC architecture on a semiconductor chip and adapted to execute a data transfer instruction, the central processing unit comprising:
 a program counter;   a plurality of registers;   wherein the data transfer instruction is of 16 bits in length and includes:
 a first field to indicate an operation code for a data transfer operation, 
 a second field to indicate a destination register which is one of the plurality of registers where data of a bit length greater than the 16 bit length is to be loaded, and 
 a third field to indicate a displacement which is utilized for indicating a first address by adding to a second address in the program counter, 
   wherein the central processing unit executes the data transfer instruction to load the data of a bit length greater than the 16 bits in length stored in the first address to the destination register.   
     
     
         12 . The central processing unit according to  claim 11 ,
 wherein the program counter is of 32 bits in length.   
     
     
         13 . The central processing unit according to  claim 11 ,
 wherein the plurality of registers are general purpose registers of 32 bits in length.   
     
     
         14 . The central processing unit according to  claim 11 ,
 wherein displacement is of 8 bits in length.   
     
     
         15 . The central processing unit according to  claim 11 ,
 wherein the data is of 32 bits in length.   
     
     
         16 . The central processing unit according to  claim 15 ,
 wherein the displacement is shifted leftward by 2 bits and the shifted displacement is added to the second address in the program counter.   
     
     
         17 . A data processor on a single semiconductor device, comprising:
 a RISC type CPU to have 32-bit general purpose registers and a program counter; and   a memory coupled to the CPU and to store instructions to be executed by the RISC type CPU,   wherein the instructions include a data transfer instruction of 16 bits in length and include:
 a first area to indicate an operation code for a data transfer operation, 
 a second area to indicate a destination register which is one of the 32-bit general purpose registers where data of 32 bits in length is to be loaded, and 
 a third area to indicate a first displacement which is used for indicating a first address by adding to a second address in the program counter, 
   wherein the RISC type CPU executes the data transfer instruction to load the data stored in the first address to the destination register.   
     
     
         18 . The data processor according to  claim 17 ,
 wherein the program counter is of 32 bits in length.   
     
     
         19 . The data processor according to  claim 17 ,
 wherein displacement is of 8 bits in length.   
     
     
         20 . The data processor according to  claim 17 ,
 wherein the displacement is shifted leftward by 2 bits and the shifted displacement is added to the second address in the program counter.   
     
     
         21 . The data processor according to  claim 17 ,
 wherein the instructions include:
 a conditional branch instruction of 16 bits in length including a fourth area to indicate a second displacement which is used for indicating a third address by adding to the second address in the program counter, and 
 an unconditional branch instruction of 16 bits in length including a fifth area indicating a third displacement which is used for indicating a fourth address by adding to the second address in the program counter, and 
   wherein a length of the fourth area is smaller than that of the fifth area.   
     
     
         22 . A microcomputer on a single semiconductor device comprising:
 a CPU having general purpose registers and a program counter;   a RAM coupled to the CPU;   a DMA controller coupled to the RAM; and   a memory coupled to the CPU and for storing instructions to be processed by the CPU;   wherein the instructions include:
 a conditional branch instruction of 16 bits in length and including a first area for a first displacement which is utilized for indicating a first branch target address by adding to a second address in the program counter, 
 an unconditional branch instruction of 16 bits in length and including a second area for a second displacement which is utilized for indicating a second branch target address by adding to the second address in the program counter and whose length is longer than that of the first area, and 
 a data transfer instruction of 16 bits in length and including a third area for a third displacement which is utilized for indicating a first address by adding to the second address in the program counter and a fourth area for a destination register information for designating one of the general purpose registers where data of 32 bits in length which is stored in the first address is loaded. 
   
     
     
         23 . The microcomputer according to  claim 22 , wherein the third area of the data transfer instruction is of 8 bits in length. 
     
     
         24 . The microcomputer according to  claim 22 , wherein the program counter is of 32 bits in length. 
     
     
         25 . The microcomputer according to  claim 22 , wherein the general purpose registers are of 32 bits in length. 
     
     
         26 . The microcomputer according to  claim 22 , wherein the first area of the conditional branch instruction is of 8 bits in length. 
     
     
         27 . The microcomputer according to  claim 22 , wherein the second area of the unconditional branch instruction is of 12 bits in length. 
     
     
         28 . The microcomputer according to  claim 22 , wherein the memory is a cache memory. 
     
     
         29 . The microcomputer according to  claim 22 , wherein the first address is obtained by adding the third displacement in the first area with the address in the program counter. 
     
     
         30 . The microcomputer according to  claim 22 ,
 wherein the data transfer instruction further includes a fifth area for an operation code defining a data transfer operation, and   wherein the third displacement is shifted leftward by 2 bits and the shifted third displacement is added to the second address in the program counter.   
     
     
         31 . A central processing unit of RISC architecture on a semiconductor chip and adapted to execute a data transfer instruction, the central processing unit comprising:
 a program counter; and   a plurality of registers,   wherein the data transfer instruction is of 16 bits in length and includes:
 a first field to indicate an operation code for a data transfer operation, 
 a second field to indicate a destination register which is one of the plurality of registers, data of a bit length being greater than the 16 bit length to be loaded in to the destination register, and 
 a third field to indicate a first displacement which is utilized for indicating a first address by adding to a second address in the program counter, 
   wherein the central processing unit executes the data transfer instruction to load the data stored in the first address to the destination register.   
     
     
         32 . The central processing unit according to  claim 31 ,
 wherein the program counter is of 32 bits in length, and   wherein the plurality of registers are of 32 bits in length.   
     
     
         33 . The central processing unit according to  claim 32 ,
 wherein the central processing unit is adapted to execute a conditional branch instruction, and   wherein the conditional branch instruction is 16 bits in length, and includes a fourth field to indicate a second displacement which is used for indicating a third address by adding to the second address in the program counter.   
     
     
         34 . The central processing unit according to  claim 33 ,
 wherein the central processing unit is adapted to execute an unconditional branch instruction, and   wherein the unconditional branch instruction is 16 bits in length, and includes a fifth field to indicate a third displacement which is used for indicating a fourth address by adding to the second address in the program counter.