Method of selective oxygen implantation to dielectricallly isolate semiconductor devices using no extra masks

Abstract

A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune.

1 . A method of fabricating isolation dielectric in an integrated circuit structure, the method comprising:
 forming a patterned mask over a p-type silicon substrate;   using the patterned mask to introduce oxygen into a first selected region of the silicon substrate, the first selected region being beneath an upper surface area of the silicon substrate that is exposed by the patterned mask;   using the patterned mask to introduce p-type dopant into a second selected region of the silicon substrate to form a p-type buried layer in the silicon substrate, the second selected region being beneath the upper surface area of the silicon substrate that is exposed by the patterned mask and above the first selected region into which the oxygen has been introduced;   performing a buried layer thermal anneal step that causes the oxygen in the first selected region to react to form a silicon oxide layer beneath the buried layer;   forming an epitaxial silicon layer over the buried layer;   forming a deep trench isolation structure in the silicon substrate that intersects with the silicon oxide layer to define an active device region that includes the buried layer and the epitaxial layer.   
   
   
       2 . The method of  claim 2 , wherein the step of forming a deep trench isolation structure comprises forming spaced-apart deep trench isolation structures that intersect with the silicon oxide layer to form a first active device region and a second active device region that is separated from the first active device region by intervening deep trench isolation structure and such that the second active device region includes a well of p-type conductivity formed therein, the method further comprising:
 forming a well of n-type conductivity in the first active device region;   forming a PMOS device structure in the n-type well; and   forming a NMOS device in the p-type well.   
   
   
       3 . A method of fabricating dielectric isolation for an integrated circuit structure, the method comprising:
 forming a patterned mask over a silicon substrate;   using the patterned mask to introduce oxygen into a selected region of the silicon substrate, the selected region having an upper surface that extends to a first depth beneath an upper surface of the silicon substrate and a lower surface that extends to a second depth beneath the upper surface of the silicon substrate, the second depth being greater than the first depth;   using the patterned mask to perform a further step in the formation of the integrated circuit structure;   performing a thermal step to cause the oxygen in the selected region of the silicon substrate to react to form a silicon oxide layer having upper and lower surfaces beneath the upper surface of the silicon substrate; and   forming a deep trench isolation structure in the silicon substrate that intersects with the silicon oxide layer to define an active device region.   
   
   
       4 . The method of  claim 3 , wherein the patterned mask comprises resist.