Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film

Abstract

A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan −1 (W2/T)<α≦tan −1 (W1/T), where W1 is an interval between a first portion and a fourth portion and an interval between a third portion and a sixth portion; W2 is an interval between a second portion and a fifth portion; T is a total film thickness of the silicon oxide film and the silicon nitride film. When the implant angle α is controlled within that range, impurity ions are implanted into a second side surface and a fifth side surface through a silicon oxide film.

1 . A method of manufacturing a semiconductor device having transistor formed on an element forming region defined by a trench isolation region, comprising:
 (a) forming a first insulating film on a main surface of a semiconductor substrate;   (b) forming a conductive film on said first insulating film;   (c) implanting first impurity ions into said main surface through said conductive film and said first insulating film to form doped channel regions of a first conductivity type;   (d) patterning said conductive film to form a gate electrode; and   (e) implanting second impurity ions into said main surface that is exposed from said gate electrode to form source and drain regions of a second conductivity type.   
     
     
         2 . The method according to  claim 1 , further comprising:
 (f) forming a second insulating film on said conductive film, said step (f) being performed between said steps (b) and (c);   (g) patterning said second insulating film, said step (g) being performed between said steps (c) and (d), wherein:   in said step (c), said first impurity ions are implanted into said main surface through said second insulating film, said conductive film and said first insulating film, and   in said step (d), said conductive film is patterned by an etch technique using said second insulating film patterned in said step (g) as an etch mask.   
     
     
         3 . The method according to  claim 1 , wherein:
 in said step (a), said first insulating film is formed using a lump oxidation apparatus at about 900 to 1100° C.   
     
     
         4 . The method according to  claim 1 , further comprising:
 (h) forming a trench in said main surface;   (i) forming a thermal oxidation film on side surfaces and a bottom surface of said trench by a thermal oxidation technique at about 900 to 1150° C., using a single wafer-type lamp oxidation apparatus; and   (j) forming a third insulation film to fill said trench;   wherein said steps (h), (i) and (j) are performed before said step (a) to form said trench isolation region.   
     
     
         5 . The method according to  claim 1 , wherein said step (c) further includes:
 (c-1) implanting third impurity ions into said main surface deeper than a bottom of said trench isolation region through said conductive film and said first insulating film to form channel well regions of said first conductivity type;   (c-2) implanting fourth impurity ions into said main surface so as to contact said bottom of said trench isolation region through said conductive film and said first insulating film to form channel cut regions of said first conductivity type.   
     
     
         6 . The method according to  claim 5 , wherein in said step (c) said first, second and third impurity ions are implanted substantially in a same region in plane view. 
     
     
         7 . The method according to  claim 1 , further comprising:
 (k) forming an interlayer insulation film after said step (e);   (l) forming a contact hole connected to said source and drain regions in said interlayer insulation film;   (m) forming a conductive plug in said contact hole;   (n) forming a lower electrode of a capacitor over said conductive plug,   (o) forming a dielectric film on said lower electrode; and   (p) forming an upper electrode of said capacitor on said dielectric film.