US2010188877A1PendingUtilityA1

Storage device

Assignee: HITACHI LTDPriority: Feb 1, 2002Filed: Mar 26, 2010Published: Jul 29, 2010
Est. expiryFeb 1, 2022(expired)· nominal 20-yr term from priority
G11C 2013/0078G11C 13/0004G11C 13/0026G11C 13/004G11C 2013/0042G11C 13/0069G11C 11/1673G11C 11/1653G11C 8/10G11C 2213/79G11C 2013/0054G11C 11/1659G11C 11/1693G11C 11/16H10B 63/10G11C 7/12H10B 63/30H10N 70/828H10N 70/8828H10B 63/80H10N 70/231H10B 63/34H10N 70/826
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Claims

Abstract

The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Claims

exact text as granted — not AI-modified
1 . A storage device comprising:
 a first metal wiring;   a second metal wiring provided over the first metal wiring; and   a memory cell coupled between the first metal wiring and the second metal wiring, and having a storage element and a selection transistor the selection transistor being coupled to the storage element in series and having a channel region made of a poly-silicon and a gate electrode,   wherein a resistance value of the storage element varies by a current flowing in the storage element,   wherein the current flowing in the storage element is controlled by a voltage of the gate electrode of the selection element.   
     
     
         2 . A storage device according to  claim 1 ,
 wherein the gate electrode of the selection element is provided at the side of the channel region of the selection element.   
     
     
         3 . A storage device according to  claim 1 ,
 wherein the selection element has two diffusion layer regions that function as source and drain region of the selection elements.   
     
     
         4 . A storage device according to  claim 3 ,
 wherein the storage element is provided on the selection element.   
     
     
         5 . A storage device according to  claim 1 , further comprising:
 a first transistor provided on the substrate,   wherein the first metal wiring is coupled to the first transistor.

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