Storage device
Abstract
The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
Claims
exact text as granted — not AI-modified1 . A storage device comprising:
a first metal wiring; a second metal wiring provided over the first metal wiring; and a memory cell coupled between the first metal wiring and the second metal wiring, and having a storage element and a selection transistor the selection transistor being coupled to the storage element in series and having a channel region made of a poly-silicon and a gate electrode, wherein a resistance value of the storage element varies by a current flowing in the storage element, wherein the current flowing in the storage element is controlled by a voltage of the gate electrode of the selection element.
2 . A storage device according to claim 1 ,
wherein the gate electrode of the selection element is provided at the side of the channel region of the selection element.
3 . A storage device according to claim 1 ,
wherein the selection element has two diffusion layer regions that function as source and drain region of the selection elements.
4 . A storage device according to claim 3 ,
wherein the storage element is provided on the selection element.
5 . A storage device according to claim 1 , further comprising:
a first transistor provided on the substrate, wherein the first metal wiring is coupled to the first transistor.Join the waitlist — get patent alerts
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